From: Jinyoung Jeon jy0.jeon@samsung.com
This patch fixed unnormal interrupt at m2m operation sometimes. m2m operation called s/w reset during every frame. but m2m occured interrupt after s/w reset sometimes. so, we cleared dma operation and capture operation.
Signed-off-by: Jinyoung Jeon jy0.jeon@samsung.com Signed-off-by: Eunchul Kim chulspro.kim@samsung.com --- drivers/gpu/drm/exynos/exynos_drm_fimc.c | 13 +++++++++++++ 1 files changed, 13 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimc.c b/drivers/gpu/drm/exynos/exynos_drm_fimc.c index 67e1b88..c9eaa81 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fimc.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fimc.c @@ -169,10 +169,23 @@ static void fimc_sw_reset(struct fimc_context *ctx)
DRM_DEBUG_KMS("%s\n", __func__);
+ /* stop dma operation */ + cfg = fimc_read(EXYNOS_CISTATUS); + if (EXYNOS_CISTATUS_GET_ENVID_STATUS(cfg)) { + cfg = fimc_read(EXYNOS_MSCTRL); + cfg &= ~EXYNOS_MSCTRL_ENVID; + fimc_write(cfg, EXYNOS_MSCTRL); + } + cfg = fimc_read(EXYNOS_CISRCFMT); cfg |= EXYNOS_CISRCFMT_ITU601_8BIT; fimc_write(cfg, EXYNOS_CISRCFMT);
+ /* disable image capture */ + cfg = fimc_read(EXYNOS_CIIMGCPT); + cfg &= ~(EXYNOS_CIIMGCPT_IMGCPTEN_SC | EXYNOS_CIIMGCPT_IMGCPTEN); + fimc_write(cfg, EXYNOS_CIIMGCPT); + /* s/w reset */ cfg = fimc_read(EXYNOS_CIGCTRL); cfg |= (EXYNOS_CIGCTRL_SWRST);