These functions mostly do the same thing so unify them. CDV include the pipe select bit in the pfit control register but we can do this on PSB as well since LVDS is always on the same pipe there. Oaktrail lvds modeset sequence is slightly different so is not unified here.
Signed-off-by: Patrik Jakobsson patrik.r.jakobsson@gmail.com --- drivers/gpu/drm/gma500/cdv_intel_lvds.c | 38 +------------------------ drivers/gpu/drm/gma500/gma_lvds.c | 35 +++++++++++++++++++++++ drivers/gpu/drm/gma500/gma_lvds.h | 3 ++ drivers/gpu/drm/gma500/psb_intel_lvds.c | 35 +---------------------- 4 files changed, 40 insertions(+), 71 deletions(-)
diff --git a/drivers/gpu/drm/gma500/cdv_intel_lvds.c b/drivers/gpu/drm/gma500/cdv_intel_lvds.c index 77a5d167c508..ddfb976b6059 100644 --- a/drivers/gpu/drm/gma500/cdv_intel_lvds.c +++ b/drivers/gpu/drm/gma500/cdv_intel_lvds.c @@ -39,42 +39,6 @@ #define PSB_BACKLIGHT_PWM_CTL_SHIFT (16) #define PSB_BACKLIGHT_PWM_POLARITY_BIT_CLEAR (0xFFFE)
-static void cdv_intel_lvds_mode_set(struct drm_encoder *encoder, - struct drm_display_mode *mode, - struct drm_display_mode *adjusted_mode) -{ - struct drm_device *dev = encoder->dev; - struct drm_psb_private *dev_priv = to_drm_psb_private(dev); - struct gma_crtc *gma_crtc = to_gma_crtc(encoder->crtc); - u32 pfit_control; - - /* - * The LVDS pin pair will already have been turned on in the - * cdv_intel_crtc_mode_set since it has a large impact on the DPLL - * settings. - */ - - /* - * Enable automatic panel scaling so that non-native modes fill the - * screen. Should be enabled before the pipe is enabled, according to - * register description and PRM. - */ - if (mode->hdisplay != adjusted_mode->hdisplay || - mode->vdisplay != adjusted_mode->vdisplay) - pfit_control = (PFIT_ENABLE | VERT_AUTO_SCALE | - HORIZ_AUTO_SCALE | VERT_INTERP_BILINEAR | - HORIZ_INTERP_BILINEAR); - else - pfit_control = 0; - - pfit_control |= gma_crtc->pipe << PFIT_PIPE_SHIFT; - - if (dev_priv->lvds_dither) - pfit_control |= PANEL_8TO6_DITHER_ENABLE; - - REG_WRITE(PFIT_CONTROL, pfit_control); -} - /* * Return the list of DDC modes if available, or the BIOS fixed mode otherwise. */ @@ -177,7 +141,7 @@ static const struct drm_encoder_helper_funcs .dpms = gma_lvds_encoder_dpms, .mode_fixup = gma_lvds_mode_fixup, .prepare = gma_lvds_prepare, - .mode_set = cdv_intel_lvds_mode_set, + .mode_set = gma_lvds_mode_set, .commit = gma_lvds_commit, };
diff --git a/drivers/gpu/drm/gma500/gma_lvds.c b/drivers/gpu/drm/gma500/gma_lvds.c index 6364d3aef064..215bf8f7d41f 100644 --- a/drivers/gpu/drm/gma500/gma_lvds.c +++ b/drivers/gpu/drm/gma500/gma_lvds.c @@ -299,3 +299,38 @@ void gma_lvds_commit(struct drm_encoder *encoder) gma_lvds_set_power(dev, true); }
+void gma_lvds_mode_set(struct drm_encoder *encoder, + struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) +{ + struct drm_device *dev = encoder->dev; + struct drm_psb_private *dev_priv = to_drm_psb_private(dev); + struct gma_crtc *gma_crtc = to_gma_crtc(encoder->crtc); + u32 pfit_control; + + /* + * The LVDS pin pair will already have been turned on in the + * *_crtc_mode_set since it has a large impact on the DPLL * settings. + */ + + /* + * Enable automatic panel scaling so that non-native modes fill the + * screen. Should be enabled before the pipe is enabled, according to + * register description and PRM. + */ + if (mode->hdisplay != adjusted_mode->hdisplay || + mode->vdisplay != adjusted_mode->vdisplay) + pfit_control = (PFIT_ENABLE | VERT_AUTO_SCALE | + HORIZ_AUTO_SCALE | VERT_INTERP_BILINEAR | + HORIZ_INTERP_BILINEAR); + else + pfit_control = 0; + + pfit_control |= gma_crtc->pipe << PFIT_PIPE_SHIFT; + + if (dev_priv->lvds_dither) + pfit_control |= PANEL_8TO6_DITHER_ENABLE; + + REG_WRITE(PFIT_CONTROL, pfit_control); +} + diff --git a/drivers/gpu/drm/gma500/gma_lvds.h b/drivers/gpu/drm/gma500/gma_lvds.h index c2c8fe5b5aac..ebba869a25b7 100644 --- a/drivers/gpu/drm/gma500/gma_lvds.h +++ b/drivers/gpu/drm/gma500/gma_lvds.h @@ -34,5 +34,8 @@ bool gma_lvds_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *adjusted_mode); void gma_lvds_prepare(struct drm_encoder *encoder); void gma_lvds_commit(struct drm_encoder *encoder); +void gma_lvds_mode_set(struct drm_encoder *encoder, + struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode);
#endif diff --git a/drivers/gpu/drm/gma500/psb_intel_lvds.c b/drivers/gpu/drm/gma500/psb_intel_lvds.c index fbb72be6e017..553f6cb5f322 100644 --- a/drivers/gpu/drm/gma500/psb_intel_lvds.c +++ b/drivers/gpu/drm/gma500/psb_intel_lvds.c @@ -132,39 +132,6 @@ void psb_intel_lvds_set_brightness(struct drm_device *dev, int level) psb_lvds_pwm_set_brightness(dev, level); }
-static void psb_intel_lvds_mode_set(struct drm_encoder *encoder, - struct drm_display_mode *mode, - struct drm_display_mode *adjusted_mode) -{ - struct drm_device *dev = encoder->dev; - struct drm_psb_private *dev_priv = to_drm_psb_private(dev); - u32 pfit_control; - - /* - * The LVDS pin pair will already have been turned on in the - * psb_intel_crtc_mode_set since it has a large impact on the DPLL - * settings. - */ - - /* - * Enable automatic panel scaling so that non-native modes fill the - * screen. Should be enabled before the pipe is enabled, according to - * register description and PRM. - */ - if (mode->hdisplay != adjusted_mode->hdisplay || - mode->vdisplay != adjusted_mode->vdisplay) - pfit_control = (PFIT_ENABLE | VERT_AUTO_SCALE | - HORIZ_AUTO_SCALE | VERT_INTERP_BILINEAR | - HORIZ_INTERP_BILINEAR); - else - pfit_control = 0; - - if (dev_priv->lvds_dither) - pfit_control |= PANEL_8TO6_DITHER_ENABLE; - - REG_WRITE(PFIT_CONTROL, pfit_control); -} - /* * Return the list of DDC modes if available, or the BIOS fixed mode otherwise. */ @@ -273,7 +240,7 @@ static const struct drm_encoder_helper_funcs psb_intel_lvds_helper_funcs = { .dpms = gma_lvds_encoder_dpms, .mode_fixup = gma_lvds_mode_fixup, .prepare = gma_lvds_prepare, - .mode_set = psb_intel_lvds_mode_set, + .mode_set = gma_lvds_mode_set, .commit = gma_lvds_commit, };