On Thu, Apr 29, 2021 at 10:12:51AM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursulin@intel.com
We distinguish masked registers from other workarounds by the mask (clr) being zero for the former.
the difference is more on the fact that those calls used _MASKED_* macros to prepare the upper 16 bits than the fact the clr is 0.
clr is zero only because for masked registers we don't care about clearing the value since all the bits in the mask will be written. More below.
To avoid callers of the low-level wa_add having to know that, and be passing this zero explicitly, add a wa_masked_add low-level helper which embeds this knowledge.
Signed-off-by: Tvrtko Ursulin tvrtko.ursulin@intel.com
drivers/gpu/drm/i915/gt/intel_workarounds.c | 56 +++++++++++++-------- 1 file changed, 34 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 62cb9ee5bfc3..a7abf9ca78ec 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -162,6 +162,18 @@ static void wa_add(struct i915_wa_list *wal, i915_reg_t reg, _wa_add(wal, &wa); }
+static void wa_masked_add(struct i915_wa_list *wal, i915_reg_t reg,
u32 set, u32 read_mask)+{
- struct i915_wa wa = {
.reg = reg,.set = set,.read = read_mask,- };
- _wa_add(wal, &wa);
+}
I think this would be better together with the other wa_masked_* functions. If not only by the name, but also because we have a comment there:
/* * WA operations on "masked register". A masked register has the upper 16 bits * documented as "masked" in b-spec. Its purpose is to allow writing to just a * portion of the register without a rmw: you simply write in the upper 16 bits * the mask of bits you are going to modify. * * The wa_masked_* family of functions already does the necessary operations to * calculate the mask based on the parameters passed, so user only has to * provide the lower 16 bits of that register. */
static void wa_write_clr_set(struct i915_wa_list *wal, i915_reg_t reg, u32 clear, u32 set) { @@ -200,20 +212,20 @@ wa_write_clr(struct i915_wa_list *wal, i915_reg_t reg, u32 clr) static void wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val) {
- wa_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val);
- wa_masked_add(wal, reg, _MASKED_BIT_ENABLE(val), val);
for me it feels weird that now we have to use wa_masked_add() *and* at the same time use _MASKED_BIT_ENABLE(). This is not the case for when we are using wa_masked_en() for example.
and as I said, the clr bits could be anything since they don't really matter. The biggest value added by the wa_masked_* variant is the use of _MASKED_* where needed.
Lucas De Marchi
}
static void wa_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val) {
- wa_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val);
- wa_masked_add(wal, reg, _MASKED_BIT_DISABLE(val), val);
}
static void wa_masked_field_set(struct i915_wa_list *wal, i915_reg_t reg, u32 mask, u32 val) {
- wa_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask);
- wa_masked_add(wal, reg, _MASKED_FIELD(mask, val), mask);
}
static void gen6_ctx_workarounds_init(struct intel_engine_cs *engine, @@ -836,10 +848,10 @@ hsw_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) /* L3 caching of data atomics doesn't work -- disable it. */ wa_write(wal, HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
- wa_add(wal,
HSW_ROW_CHICKEN3, 0,_MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE),0 /* XXX does this reg exist? */);
wa_masked_add(wal,
HSW_ROW_CHICKEN3,_MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE),0 /* XXX does this reg exist? */);/* WaVSRefCountFullforceMissDisable:hsw */ wa_write_clr(wal, GEN7_FF_THREAD_MODE, GEN7_FF_VS_REF_CNT_FFME);
@@ -1947,10 +1959,10 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) * disable bit, which we don't touch here, but it's good * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). */
wa_add(wal, GEN7_GT_MODE, 0,_MASKED_FIELD(GEN6_WIZ_HASHING_MASK,GEN6_WIZ_HASHING_16x4),GEN6_WIZ_HASHING_16x4);
wa_masked_field_set(wal,GEN7_GT_MODE,GEN6_WIZ_HASHING_MASK,GEN6_WIZ_HASHING_16x4);}
if (IS_GEN_RANGE(i915, 6, 7))
@@ -2000,10 +2012,10 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) * disable bit, which we don't touch here, but it's good * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). */
wa_add(wal,GEN6_GT_MODE, 0,_MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4),GEN6_WIZ_HASHING_16x4);
wa_masked_field_set(wal,GEN6_GT_MODE,GEN6_WIZ_HASHING_MASK,GEN6_WIZ_HASHING_16x4);/* WaDisable_RenderCache_OperationalFlush:snb */ wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE);
@@ -2021,10 +2033,10 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
if (IS_GEN_RANGE(i915, 4, 6)) /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
wa_add(wal, MI_MODE,0, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH),/* XXX bit doesn't stick on Broadwater */IS_I965G(i915) ? 0 : VS_TIMER_DISPATCH);
wa_masked_add(wal, MI_MODE,_MASKED_BIT_ENABLE(VS_TIMER_DISPATCH),/* XXX bit doesn't stick on Broadwater */IS_I965G(i915) ? 0 : VS_TIMER_DISPATCH);if (IS_GEN(i915, 4)) /*
@@ -2037,9 +2049,9 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) * they are already accustomed to from before contexts were * enabled. */
wa_add(wal, ECOSKPD,0, _MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE),0 /* XXX bit doesn't stick on Broadwater */);
wa_masked_add(wal, ECOSKPD,_MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE),0 /* XXX bit doesn't stick on Broadwater */);}
static void
2.30.2
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