From: Tvrtko Ursulin tvrtko.ursulin@intel.com
Some cleanups and improvements to checks being done when building workaround lists. First five patches are small cleanups while the last one contains the actual story of what gets improved.
Test-with: 20210429084130.850426-1-tvrtko.ursulin@linux.intel.com
Tvrtko Ursulin (6): drm/i915: Drop duplicate WaDisable4x2SubspanOptimization:hsw drm/i915/debugfs: Expose read mask in i915_wa_registers drm/i915: Add a separate low-level helper for masked workarounds drm/i915/icl: Use appropriate helper for a masked workaround drm/i915/icl: Stop conflating mask and readback verify drm/i915: Add more checks when building workaround lists
drivers/gpu/drm/i915/gt/intel_workarounds.c | 163 +++++++++++++----- .../gpu/drm/i915/gt/intel_workarounds_types.h | 4 + .../gpu/drm/i915/gt/selftest_workarounds.c | 4 +- drivers/gpu/drm/i915/i915_debugfs.c | 4 +- 4 files changed, 124 insertions(+), 51 deletions(-)
From: Tvrtko Ursulin tvrtko.ursulin@intel.com
Same workaround was listed two times - once under the Gen7 block and once under the Haswell section.
Signed-off-by: Tvrtko Ursulin tvrtko.ursulin@intel.com --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 --- 1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 5a03a76bb9e2..62cb9ee5bfc3 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -1859,9 +1859,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) CACHE_MODE_0_GEN7, /* enable HiZ Raw Stall Optimization */ HIZ_RAW_STALL_OPT_DISABLE); - - /* WaDisable4x2SubspanOptimization:hsw */ - wa_masked_en(wal, CACHE_MODE_1, PIXEL_SUBSPAN_COLLECT_OPT_DISABLE); }
if (IS_VALLEYVIEW(i915)) {
On Thu, Apr 29, 2021 at 10:12:49AM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursulin@intel.com
Same workaround was listed two times - once under the Gen7 block and once under the Haswell section.
Signed-off-by: Tvrtko Ursulin tvrtko.ursulin@intel.com
Reviewed-by: Lucas De Marchi lucas.demarchi@intel.com
Lucas De Marchi
drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 --- 1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 5a03a76bb9e2..62cb9ee5bfc3 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -1859,9 +1859,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) CACHE_MODE_0_GEN7, /* enable HiZ Raw Stall Optimization */ HIZ_RAW_STALL_OPT_DISABLE);
/* WaDisable4x2SubspanOptimization:hsw */wa_masked_en(wal, CACHE_MODE_1, PIXEL_SUBSPAN_COLLECT_OPT_DISABLE);}
if (IS_VALLEYVIEW(i915)) {
-- 2.30.2
Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
From: Tvrtko Ursulin tvrtko.ursulin@intel.com
In order to stop conflating the validation via readback with the workaround mask I need to expose the read mask separately so gem_workarounds IGT can continue operating correctly.
Signed-off-by: Tvrtko Ursulin tvrtko.ursulin@intel.com --- drivers/gpu/drm/i915/i915_debugfs.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 8dd374691102..b9c81376a413 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -757,9 +757,9 @@ static int i915_wa_registers(struct seq_file *m, void *unused) engine->name, count);
for (wa = wal->list; count--; wa++) - seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X\n", + seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08X\n", i915_mmio_reg_offset(wa->reg), - wa->set, wa->clr); + wa->set, wa->clr, wa->read);
seq_printf(m, "\n"); }
On Thu, Apr 29, 2021 at 10:12:50AM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursulin@intel.com
In order to stop conflating the validation via readback with the workaround mask I need to expose the read mask separately so gem_workarounds IGT can continue operating correctly.
Signed-off-by: Tvrtko Ursulin tvrtko.ursulin@intel.com
Reviewed-by: Lucas De Marchi lucas.demarchi@intel.com
Lucas De Marchi
drivers/gpu/drm/i915/i915_debugfs.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 8dd374691102..b9c81376a413 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -757,9 +757,9 @@ static int i915_wa_registers(struct seq_file *m, void *unused) engine->name, count);
for (wa = wal->list; count--; wa++)
seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X\n",
seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08X\n", i915_mmio_reg_offset(wa->reg),
wa->set, wa->clr);
wa->set, wa->clr, wa->read);seq_printf(m, "\n"); }
-- 2.30.2
Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
From: Tvrtko Ursulin tvrtko.ursulin@intel.com
We distinguish masked registers from other workarounds by the mask (clr) being zero for the former.
To avoid callers of the low-level wa_add having to know that, and be passing this zero explicitly, add a wa_masked_add low-level helper which embeds this knowledge.
Signed-off-by: Tvrtko Ursulin tvrtko.ursulin@intel.com --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 56 +++++++++++++-------- 1 file changed, 34 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 62cb9ee5bfc3..a7abf9ca78ec 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -162,6 +162,18 @@ static void wa_add(struct i915_wa_list *wal, i915_reg_t reg, _wa_add(wal, &wa); }
+static void wa_masked_add(struct i915_wa_list *wal, i915_reg_t reg, + u32 set, u32 read_mask) +{ + struct i915_wa wa = { + .reg = reg, + .set = set, + .read = read_mask, + }; + + _wa_add(wal, &wa); +} + static void wa_write_clr_set(struct i915_wa_list *wal, i915_reg_t reg, u32 clear, u32 set) { @@ -200,20 +212,20 @@ wa_write_clr(struct i915_wa_list *wal, i915_reg_t reg, u32 clr) static void wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val) { - wa_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val); + wa_masked_add(wal, reg, _MASKED_BIT_ENABLE(val), val); }
static void wa_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val) { - wa_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val); + wa_masked_add(wal, reg, _MASKED_BIT_DISABLE(val), val); }
static void wa_masked_field_set(struct i915_wa_list *wal, i915_reg_t reg, u32 mask, u32 val) { - wa_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask); + wa_masked_add(wal, reg, _MASKED_FIELD(mask, val), mask); }
static void gen6_ctx_workarounds_init(struct intel_engine_cs *engine, @@ -836,10 +848,10 @@ hsw_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) /* L3 caching of data atomics doesn't work -- disable it. */ wa_write(wal, HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
- wa_add(wal, - HSW_ROW_CHICKEN3, 0, - _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE), - 0 /* XXX does this reg exist? */); + wa_masked_add(wal, + HSW_ROW_CHICKEN3, + _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE), + 0 /* XXX does this reg exist? */);
/* WaVSRefCountFullforceMissDisable:hsw */ wa_write_clr(wal, GEN7_FF_THREAD_MODE, GEN7_FF_VS_REF_CNT_FFME); @@ -1947,10 +1959,10 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) * disable bit, which we don't touch here, but it's good * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). */ - wa_add(wal, GEN7_GT_MODE, 0, - _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, - GEN6_WIZ_HASHING_16x4), - GEN6_WIZ_HASHING_16x4); + wa_masked_field_set(wal, + GEN7_GT_MODE, + GEN6_WIZ_HASHING_MASK, + GEN6_WIZ_HASHING_16x4); }
if (IS_GEN_RANGE(i915, 6, 7)) @@ -2000,10 +2012,10 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) * disable bit, which we don't touch here, but it's good * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). */ - wa_add(wal, - GEN6_GT_MODE, 0, - _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4), - GEN6_WIZ_HASHING_16x4); + wa_masked_field_set(wal, + GEN6_GT_MODE, + GEN6_WIZ_HASHING_MASK, + GEN6_WIZ_HASHING_16x4);
/* WaDisable_RenderCache_OperationalFlush:snb */ wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE); @@ -2021,10 +2033,10 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
if (IS_GEN_RANGE(i915, 4, 6)) /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ - wa_add(wal, MI_MODE, - 0, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH), - /* XXX bit doesn't stick on Broadwater */ - IS_I965G(i915) ? 0 : VS_TIMER_DISPATCH); + wa_masked_add(wal, MI_MODE, + _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH), + /* XXX bit doesn't stick on Broadwater */ + IS_I965G(i915) ? 0 : VS_TIMER_DISPATCH);
if (IS_GEN(i915, 4)) /* @@ -2037,9 +2049,9 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) * they are already accustomed to from before contexts were * enabled. */ - wa_add(wal, ECOSKPD, - 0, _MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE), - 0 /* XXX bit doesn't stick on Broadwater */); + wa_masked_add(wal, ECOSKPD, + _MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE), + 0 /* XXX bit doesn't stick on Broadwater */); }
static void
On Thu, Apr 29, 2021 at 10:12:51AM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursulin@intel.com
We distinguish masked registers from other workarounds by the mask (clr) being zero for the former.
the difference is more on the fact that those calls used _MASKED_* macros to prepare the upper 16 bits than the fact the clr is 0.
clr is zero only because for masked registers we don't care about clearing the value since all the bits in the mask will be written. More below.
To avoid callers of the low-level wa_add having to know that, and be passing this zero explicitly, add a wa_masked_add low-level helper which embeds this knowledge.
Signed-off-by: Tvrtko Ursulin tvrtko.ursulin@intel.com
drivers/gpu/drm/i915/gt/intel_workarounds.c | 56 +++++++++++++-------- 1 file changed, 34 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 62cb9ee5bfc3..a7abf9ca78ec 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -162,6 +162,18 @@ static void wa_add(struct i915_wa_list *wal, i915_reg_t reg, _wa_add(wal, &wa); }
+static void wa_masked_add(struct i915_wa_list *wal, i915_reg_t reg,
u32 set, u32 read_mask)+{
- struct i915_wa wa = {
.reg = reg,.set = set,.read = read_mask,- };
- _wa_add(wal, &wa);
+}
I think this would be better together with the other wa_masked_* functions. If not only by the name, but also because we have a comment there:
/* * WA operations on "masked register". A masked register has the upper 16 bits * documented as "masked" in b-spec. Its purpose is to allow writing to just a * portion of the register without a rmw: you simply write in the upper 16 bits * the mask of bits you are going to modify. * * The wa_masked_* family of functions already does the necessary operations to * calculate the mask based on the parameters passed, so user only has to * provide the lower 16 bits of that register. */
static void wa_write_clr_set(struct i915_wa_list *wal, i915_reg_t reg, u32 clear, u32 set) { @@ -200,20 +212,20 @@ wa_write_clr(struct i915_wa_list *wal, i915_reg_t reg, u32 clr) static void wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val) {
- wa_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val);
- wa_masked_add(wal, reg, _MASKED_BIT_ENABLE(val), val);
for me it feels weird that now we have to use wa_masked_add() *and* at the same time use _MASKED_BIT_ENABLE(). This is not the case for when we are using wa_masked_en() for example.
and as I said, the clr bits could be anything since they don't really matter. The biggest value added by the wa_masked_* variant is the use of _MASKED_* where needed.
Lucas De Marchi
}
static void wa_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val) {
- wa_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val);
- wa_masked_add(wal, reg, _MASKED_BIT_DISABLE(val), val);
}
static void wa_masked_field_set(struct i915_wa_list *wal, i915_reg_t reg, u32 mask, u32 val) {
- wa_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask);
- wa_masked_add(wal, reg, _MASKED_FIELD(mask, val), mask);
}
static void gen6_ctx_workarounds_init(struct intel_engine_cs *engine, @@ -836,10 +848,10 @@ hsw_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) /* L3 caching of data atomics doesn't work -- disable it. */ wa_write(wal, HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
- wa_add(wal,
HSW_ROW_CHICKEN3, 0,_MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE),0 /* XXX does this reg exist? */);
wa_masked_add(wal,
HSW_ROW_CHICKEN3,_MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE),0 /* XXX does this reg exist? */);/* WaVSRefCountFullforceMissDisable:hsw */ wa_write_clr(wal, GEN7_FF_THREAD_MODE, GEN7_FF_VS_REF_CNT_FFME);
@@ -1947,10 +1959,10 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) * disable bit, which we don't touch here, but it's good * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). */
wa_add(wal, GEN7_GT_MODE, 0,_MASKED_FIELD(GEN6_WIZ_HASHING_MASK,GEN6_WIZ_HASHING_16x4),GEN6_WIZ_HASHING_16x4);
wa_masked_field_set(wal,GEN7_GT_MODE,GEN6_WIZ_HASHING_MASK,GEN6_WIZ_HASHING_16x4);}
if (IS_GEN_RANGE(i915, 6, 7))
@@ -2000,10 +2012,10 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) * disable bit, which we don't touch here, but it's good * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). */
wa_add(wal,GEN6_GT_MODE, 0,_MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4),GEN6_WIZ_HASHING_16x4);
wa_masked_field_set(wal,GEN6_GT_MODE,GEN6_WIZ_HASHING_MASK,GEN6_WIZ_HASHING_16x4);/* WaDisable_RenderCache_OperationalFlush:snb */ wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE);
@@ -2021,10 +2033,10 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
if (IS_GEN_RANGE(i915, 4, 6)) /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
wa_add(wal, MI_MODE,0, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH),/* XXX bit doesn't stick on Broadwater */IS_I965G(i915) ? 0 : VS_TIMER_DISPATCH);
wa_masked_add(wal, MI_MODE,_MASKED_BIT_ENABLE(VS_TIMER_DISPATCH),/* XXX bit doesn't stick on Broadwater */IS_I965G(i915) ? 0 : VS_TIMER_DISPATCH);if (IS_GEN(i915, 4)) /*
@@ -2037,9 +2049,9 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) * they are already accustomed to from before contexts were * enabled. */
wa_add(wal, ECOSKPD,0, _MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE),0 /* XXX bit doesn't stick on Broadwater */);
wa_masked_add(wal, ECOSKPD,_MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE),0 /* XXX bit doesn't stick on Broadwater */);}
static void
2.30.2
dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
On 01/05/2021 07:55, Lucas De Marchi wrote:
On Thu, Apr 29, 2021 at 10:12:51AM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursulin@intel.com
We distinguish masked registers from other workarounds by the mask (clr) being zero for the former.
the difference is more on the fact that those calls used _MASKED_* macros to prepare the upper 16 bits than the fact the clr is 0.
clr is zero only because for masked registers we don't care about clearing the value since all the bits in the mask will be written. More below.
Yes, but not only don't care but really don't want to do rmw. We have two separate paths in the apply side which is picked based on clr being zero or not.
To avoid callers of the low-level wa_add having to know that, and be passing this zero explicitly, add a wa_masked_add low-level helper which embeds this knowledge.
Signed-off-by: Tvrtko Ursulin tvrtko.ursulin@intel.com
drivers/gpu/drm/i915/gt/intel_workarounds.c | 56 +++++++++++++-------- 1 file changed, 34 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 62cb9ee5bfc3..a7abf9ca78ec 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -162,6 +162,18 @@ static void wa_add(struct i915_wa_list *wal, i915_reg_t reg, _wa_add(wal, &wa); }
+static void wa_masked_add(struct i915_wa_list *wal, i915_reg_t reg, + u32 set, u32 read_mask) +{ + struct i915_wa wa = { + .reg = reg, + .set = set, + .read = read_mask, + };
+ _wa_add(wal, &wa); +}
I think this would be better together with the other wa_masked_* functions. If not only by the name, but also because we have a comment there:
/* * WA operations on "masked register". A masked register has the upper 16 bits * documented as "masked" in b-spec. Its purpose is to allow writing to just a * portion of the register without a rmw: you simply write in the upper 16 bits * the mask of bits you are going to modify. * * The wa_masked_* family of functions already does the necessary operations to * calculate the mask based on the parameters passed, so user only has to * provide the lower 16 bits of that register. */
Yep thanks.
static void wa_write_clr_set(struct i915_wa_list *wal, i915_reg_t reg, u32 clear, u32 set) { @@ -200,20 +212,20 @@ wa_write_clr(struct i915_wa_list *wal, i915_reg_t reg, u32 clr) static void wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val) { - wa_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val); + wa_masked_add(wal, reg, _MASKED_BIT_ENABLE(val), val);
for me it feels weird that now we have to use wa_masked_add() *and* at the same time use _MASKED_BIT_ENABLE(). This is not the case for when we are using wa_masked_en() for example.
and as I said, the clr bits could be anything since they don't really matter. The biggest value added by the wa_masked_* variant is the use of _MASKED_* where needed.
Yes I wasn't fully happy with it.
How about both wa_add and wa_masked_add get a single or double underscore prefix? That would signify them being low-level and justify the need for explicitly using _MASKED_BIT_ENABLE?
Regards,
Tvrtko
Lucas De Marchi
}
static void wa_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val) { - wa_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val); + wa_masked_add(wal, reg, _MASKED_BIT_DISABLE(val), val); }
static void wa_masked_field_set(struct i915_wa_list *wal, i915_reg_t reg, u32 mask, u32 val) { - wa_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask); + wa_masked_add(wal, reg, _MASKED_FIELD(mask, val), mask); }
static void gen6_ctx_workarounds_init(struct intel_engine_cs *engine, @@ -836,10 +848,10 @@ hsw_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) /* L3 caching of data atomics doesn't work -- disable it. */ wa_write(wal, HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
- wa_add(wal, - HSW_ROW_CHICKEN3, 0,
_MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE), - 0 /* XXX does this reg exist? */); + wa_masked_add(wal, + HSW_ROW_CHICKEN3,
_MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE), + 0 /* XXX does this reg exist? */);
/* WaVSRefCountFullforceMissDisable:hsw */ wa_write_clr(wal, GEN7_FF_THREAD_MODE, GEN7_FF_VS_REF_CNT_FFME); @@ -1947,10 +1959,10 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) * disable bit, which we don't touch here, but it's good * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). */ - wa_add(wal, GEN7_GT_MODE, 0, - _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, - GEN6_WIZ_HASHING_16x4), - GEN6_WIZ_HASHING_16x4); + wa_masked_field_set(wal, + GEN7_GT_MODE, + GEN6_WIZ_HASHING_MASK, + GEN6_WIZ_HASHING_16x4); }
if (IS_GEN_RANGE(i915, 6, 7)) @@ -2000,10 +2012,10 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) * disable bit, which we don't touch here, but it's good * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). */ - wa_add(wal, - GEN6_GT_MODE, 0, - _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4), - GEN6_WIZ_HASHING_16x4); + wa_masked_field_set(wal, + GEN6_GT_MODE, + GEN6_WIZ_HASHING_MASK, + GEN6_WIZ_HASHING_16x4);
/* WaDisable_RenderCache_OperationalFlush:snb */ wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE); @@ -2021,10 +2033,10 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
if (IS_GEN_RANGE(i915, 4, 6)) /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ - wa_add(wal, MI_MODE, - 0, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH), - /* XXX bit doesn't stick on Broadwater */ - IS_I965G(i915) ? 0 : VS_TIMER_DISPATCH); + wa_masked_add(wal, MI_MODE, + _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH), + /* XXX bit doesn't stick on Broadwater */ + IS_I965G(i915) ? 0 : VS_TIMER_DISPATCH);
if (IS_GEN(i915, 4)) /* @@ -2037,9 +2049,9 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) * they are already accustomed to from before contexts were * enabled. */ - wa_add(wal, ECOSKPD, - 0, _MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE), - 0 /* XXX bit doesn't stick on Broadwater */); + wa_masked_add(wal, ECOSKPD, + _MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE), + 0 /* XXX bit doesn't stick on Broadwater */); }
static void
2.30.2
dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
From: Tvrtko Ursulin tvrtko.ursulin@intel.com
Instead of "open coding" WaEnableFloatBlendOptimization:icl via wa_write_clr_set, which should be for non-masked workarounds, add a new helper wa_masked_en_no_verify and use it.
Signed-off-by: Tvrtko Ursulin tvrtko.ursulin@intel.com --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index a7abf9ca78ec..07579bb9b6a7 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -215,6 +215,12 @@ wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val) wa_masked_add(wal, reg, _MASKED_BIT_ENABLE(val), val); }
+static void +wa_masked_en_no_verify(struct i915_wa_list *wal, i915_reg_t reg, u32 val) +{ + wa_masked_add(wal, reg, _MASKED_BIT_ENABLE(val), 0); +} + static void wa_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val) { @@ -595,10 +601,9 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine, GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC);
/* WaEnableFloatBlendOptimization:icl */ - wa_write_clr_set(wal, - GEN10_CACHE_MODE_SS, - 0, /* write-only, so skip validation */ - _MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE)); + wa_masked_en_no_verify(wal, + GEN10_CACHE_MODE_SS, + FLOAT_BLEND_OPTIMIZATION_ENABLE);
/* WaDisableGPGPUMidThreadPreemption:icl */ wa_masked_field_set(wal, GEN8_CS_CHICKEN1,
From: Tvrtko Ursulin tvrtko.ursulin@intel.com
Add a new helper wa_write_no_verify for Wa_1604278689:icl,ehl which is a write only register. This allows the mask to correctly reflect what bits the workaround writes versus which bits it will verify during read- back. In turn this will allow more safety checks to be added in a following patch.
Signed-off-by: Tvrtko Ursulin tvrtko.ursulin@intel.com --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 07579bb9b6a7..cd84c2a86787 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -186,6 +186,12 @@ wa_write(struct i915_wa_list *wal, i915_reg_t reg, u32 set) wa_write_clr_set(wal, reg, ~0, set); }
+static void +wa_write_no_verify(struct i915_wa_list *wal, i915_reg_t reg, u32 set) +{ + wa_add(wal, reg, ~0, set, 0); +} + static void wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 set) { @@ -616,9 +622,7 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
/* Wa_1604278689:icl,ehl */ wa_write(wal, IVB_FBC_RT_BASE, 0xFFFFFFFF & ~ILK_FBC_RT_VALID); - wa_write_clr_set(wal, IVB_FBC_RT_BASE_UPPER, - 0, /* write-only register; skip validation */ - 0xFFFFFFFF); + wa_write_no_verify(wal, IVB_FBC_RT_BASE_UPPER, 0xFFFFFFFF);
/* Wa_1406306137:icl,ehl */ wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN11_DIS_PICK_2ND_EU);
From: Tvrtko Ursulin tvrtko.ursulin@intel.com
In current code we check that a workaround is not completely overwriting the existing one, but for instance partial conflict in some bits would get missed, as would problems involving masked registers, courtesy of the mask (wa->clr) being forced to zero for such registers and also being conflated with the readback verification.
Now that previous patches have separated write masks from readback masks, and ensured all masked registers are correctly tagged as such, we can improve the verification checks to also detect partial conflicts, wrong masks and inconsistent register usage.
Signed-off-by: Tvrtko Ursulin tvrtko.ursulin@intel.com Reported-by: Andres Calderon Jaramillo andrescj@google.com --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 81 +++++++++++++++---- .../gpu/drm/i915/gt/intel_workarounds_types.h | 4 + .../gpu/drm/i915/gt/selftest_workarounds.c | 4 +- 3 files changed, 72 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index cd84c2a86787..c82f165bdd8b 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -52,8 +52,11 @@ * - Public functions to init or apply the given workaround type. */
-static void wa_init_start(struct i915_wa_list *wal, const char *name, const char *engine_name) +static void +wa_init_start(struct drm_i915_private *i915, struct i915_wa_list *wal, + const char *name, const char *engine_name) { + wal->i915 = i915; wal->name = name; wal->engine_name = engine_name; } @@ -81,6 +84,59 @@ static void wa_init_finish(struct i915_wa_list *wal) wal->wa_count, wal->name, wal->engine_name); }
+static void +log_bad_wa(const struct i915_wa_list *wal, const struct i915_wa *wa, + const char *msg) +{ + drm_err(&wal->i915->drm, + "Discarding %s workaround! (reg=%x %s=%x set=%x)\n", + msg, i915_mmio_reg_offset(wa->reg), wa->clr ? "clear" : "mask", + wa->clr ?: wa->set >> 16, wa->set); +} + +static bool +check_conflict(const struct i915_wa_list *wal, + const struct i915_wa *old, + const struct i915_wa *new) +{ + u32 new_mask, old_mask, common, new_set, old_set; + + if (new->clr && !old->clr) { + log_bad_wa(wal, new, "mixed masked and regular"); + return true; + } + + if (new->clr) { + new_mask = new->clr; + old_mask = old->clr; + new_set = new->set; + old_set = old->set; + } else { + new_mask = new->set >> 16; + old_mask = old->set >> 16; + new_set = new->set & 0xffff; + old_set = old->set & 0xffff; + } + + if (new_set && (new_set & ~new_mask)) { + log_bad_wa(wal, new, "write outside the mask"); + return true; + } + + common = new_mask & old_mask; + if (common) { + if ((new_set & common) != (old_set & common)) { + log_bad_wa(wal, new, "conflicting"); + return true; + } else if (new_mask == old_mask) { + log_bad_wa(wal, new, "duplicate"); + return true; + } + } + + return false; +} + static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa) { unsigned int addr = i915_mmio_reg_offset(wa->reg); @@ -118,18 +174,13 @@ static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa) } else { wa_ = &wal->list[mid];
- if ((wa->clr | wa_->clr) && !(wa->clr & ~wa_->clr)) { - DRM_ERROR("Discarding overwritten w/a for reg %04x (clear: %08x, set: %08x)\n", - i915_mmio_reg_offset(wa_->reg), - wa_->clr, wa_->set); - - wa_->set &= ~wa->clr; + if (!check_conflict(wal, wa_, wa)) { + wal->wa_count++; + wa_->set |= wa->set; + wa_->clr |= wa->clr; + wa_->read |= wa->read; }
- wal->wa_count++; - wa_->set |= wa->set; - wa_->clr |= wa->clr; - wa_->read |= wa->read; return; } } @@ -716,7 +767,7 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine, if (engine->class != RENDER_CLASS) return;
- wa_init_start(wal, name, engine->name); + wa_init_start(engine->i915, wal, name, engine->name);
if (IS_DG1(i915)) dg1_ctx_workarounds_init(engine, wal); @@ -1232,7 +1283,7 @@ void intel_gt_init_workarounds(struct drm_i915_private *i915) { struct i915_wa_list *wal = &i915->gt_wa_list;
- wa_init_start(wal, "GT", "global"); + wa_init_start(i915, wal, "GT", "global"); gt_init_workarounds(i915, wal); wa_init_finish(wal); } @@ -1575,7 +1626,7 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine) struct drm_i915_private *i915 = engine->i915; struct i915_wa_list *w = &engine->whitelist;
- wa_init_start(w, "whitelist", engine->name); + wa_init_start(engine->i915, w, "whitelist", engine->name);
if (IS_DG1(i915)) dg1_whitelist_build(engine); @@ -2095,7 +2146,7 @@ void intel_engine_init_workarounds(struct intel_engine_cs *engine) if (INTEL_GEN(engine->i915) < 4) return;
- wa_init_start(wal, "engine", engine->name); + wa_init_start(engine->i915, wal, "engine", engine->name); engine_init_workarounds(engine, wal); wa_init_finish(wal); } diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds_types.h b/drivers/gpu/drm/i915/gt/intel_workarounds_types.h index c214111ea367..b6a9d1582a5c 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds_types.h +++ b/drivers/gpu/drm/i915/gt/intel_workarounds_types.h @@ -10,6 +10,8 @@
#include "i915_reg.h"
+struct drm_i915_private; + struct i915_wa { i915_reg_t reg; u32 clr; @@ -18,6 +20,8 @@ struct i915_wa { };
struct i915_wa_list { + struct drm_i915_private *i915; + const char *name; const char *engine_name; struct i915_wa *list; diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c b/drivers/gpu/drm/i915/gt/selftest_workarounds.c index 64937ec3f2dc..536cbe7889cc 100644 --- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c +++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c @@ -64,14 +64,14 @@ reference_lists_init(struct intel_gt *gt, struct wa_lists *lists)
memset(lists, 0, sizeof(*lists));
- wa_init_start(&lists->gt_wa_list, "GT_REF", "global"); + wa_init_start(gt->i915, &lists->gt_wa_list, "GT_REF", "global"); gt_init_workarounds(gt->i915, &lists->gt_wa_list); wa_init_finish(&lists->gt_wa_list);
for_each_engine(engine, gt, id) { struct i915_wa_list *wal = &lists->engine[id].wa_list;
- wa_init_start(wal, "REF", engine->name); + wa_init_start(gt->i915, wal, "REF", engine->name); engine_init_workarounds(engine, wal); wa_init_finish(wal);
dri-devel@lists.freedesktop.org
-
Lucas De Marchi -
Tvrtko Ursulin