This patch series re-work a few i915 functions to use drm_clflush_virt_range instead of calling clflush or clflushopt directly. This will prevent errors when building for non-x86 architectures.
v2: s/PAGE_SIZE/sizeof(value) for Re-work intel_write_status_page and added more patches to convert additional clflush/clflushopt to use drm_clflush*. (Michael Cheng)
v3: Drop invalidate_csb_entries and directly invoke drm_clflush_virt_ran
v4: Remove extra memory barriers
v5: s/cache_clflush_range/drm_clflush_virt_range
v6: Fix up "Drop invalidate_csb_entries" to use correct parameters. Also added in arm64 support for drm_clflush_virt_range.
Michael Cheng (6): drm/i915/gt: Re-work intel_write_status_page drm/i915/gt: Drop invalidate_csb_entries drm/i915/gt: Re-work reset_csb drm/i915/: Re-work clflush_write32 drm/i915/gt: replace cache_clflush_range drm: Add arch arm64 for drm_clflush_virt_range
drivers/gpu/drm/drm_cache.c | 4 ++++ .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 8 +++----- drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 12 ++++++------ drivers/gpu/drm/i915/gt/intel_engine.h | 13 ++++--------- .../drm/i915/gt/intel_execlists_submission.c | 19 ++++++------------- drivers/gpu/drm/i915/gt/intel_gtt.c | 2 +- drivers/gpu/drm/i915/gt/intel_ppgtt.c | 2 +- .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +- 8 files changed, 26 insertions(+), 36 deletions(-)
Re-work intel_write_status_page to use drm_clflush_virt_range. This will prevent compiler errors when building for non-x86 architectures.
Signed-off-by: Michael Cheng michael.cheng@intel.com --- drivers/gpu/drm/i915/gt/intel_engine.h | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h index 0e353d8c2bc8..986777c2430d 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine.h +++ b/drivers/gpu/drm/i915/gt/intel_engine.h @@ -4,6 +4,7 @@
#include <asm/cacheflush.h> #include <drm/drm_util.h> +#include <drm/drm_cache.h>
#include <linux/hashtable.h> #include <linux/irq_work.h> @@ -143,15 +144,9 @@ intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value) * of extra paranoia to try and ensure that the HWS takes the value * we give and that it doesn't end up trapped inside the CPU! */ - if (static_cpu_has(X86_FEATURE_CLFLUSH)) { - mb(); - clflush(&engine->status_page.addr[reg]); - engine->status_page.addr[reg] = value; - clflush(&engine->status_page.addr[reg]); - mb(); - } else { - WRITE_ONCE(engine->status_page.addr[reg], value); - } + drm_clflush_virt_range(&engine->status_page.addr[reg], sizeof(value)); + WRITE_ONCE(engine->status_page.addr[reg], value); + drm_clflush_virt_range(&engine->status_page.addr[reg], sizeof(value)); }
/*
Drop invalidate_csb_entries and directly call drm_clflush_virt_range. This allows for one less function call, and prevent complier errors when building for non-x86 architectures.
v2(Michael Cheng): Drop invalidate_csb_entries function and directly invoke drm_clflush_virt_range. Thanks to Tvrtko for the sugguestion.
v3(Michael Cheng): Use correct parameters for drm_clflush_virt_range. Thanks to Tvrtko for pointing this out.
Signed-off-by: Michael Cheng michael.cheng@intel.com --- drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c index 9bb7c863172f..28f2581d3046 100644 --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c @@ -1646,12 +1646,6 @@ cancel_port_requests(struct intel_engine_execlists * const execlists, return inactive; }
-static void invalidate_csb_entries(const u64 *first, const u64 *last) -{ - clflush((void *)first); - clflush((void *)last); -} - /* * Starting with Gen12, the status has a new format: * @@ -1999,7 +1993,7 @@ process_csb(struct intel_engine_cs *engine, struct i915_request **inactive) * the wash as hardware, working or not, will need to do the * invalidation before. */ - invalidate_csb_entries(&buf[0], &buf[num_entries - 1]); + drm_clflush_virt_range(&buf[0], num_entries * sizeof(buf[0]));
/* * We assume that any event reflects a change in context flow @@ -2783,8 +2777,8 @@ static void reset_csb_pointers(struct intel_engine_cs *engine)
/* Check that the GPU does indeed update the CSB entries! */ memset(execlists->csb_status, -1, (reset_value + 1) * sizeof(u64)); - invalidate_csb_entries(&execlists->csb_status[0], - &execlists->csb_status[reset_value]); + drm_clflush_virt_range(&execlists->csb_status[0], + execlists->csb_size * sizeof(execlists->csb_status[0]));
/* Once more for luck and our trusty paranoia */ ENGINE_WRITE(engine, RING_CONTEXT_STATUS_PTR,
Use drm_clflush_virt_range instead of directly invoking clflush. This will prevent compiler errors when building for non-x86 architectures.
v2(Michael Cheng): Remove extra clflush
v3(Michael Cheng): Remove memory barrier since drm_clflush_virt_range takes care of it.
Signed-off-by: Michael Cheng michael.cheng@intel.com --- drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c index 28f2581d3046..cc561cfae808 100644 --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c @@ -2944,9 +2944,8 @@ reset_csb(struct intel_engine_cs *engine, struct i915_request **inactive) { struct intel_engine_execlists * const execlists = &engine->execlists;
- mb(); /* paranoia: read the CSB pointers from after the reset */ - clflush(execlists->csb_write); - mb(); + drm_clflush_virt_range(execlists->csb_write, + sizeof(execlists->csb_write));
inactive = process_csb(engine, inactive); /* drain preemption events */
Use drm_clflush_virt_range instead of clflushopt and remove the memory barrier, since drm_clflush_virt_range takes care of that.
Signed-off-by: Michael Cheng michael.cheng@intel.com --- drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index 498b458fd784..0854276ff7ba 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -1332,10 +1332,8 @@ static void *reloc_vaddr(struct i915_vma *vma, static void clflush_write32(u32 *addr, u32 value, unsigned int flushes) { if (unlikely(flushes & (CLFLUSH_BEFORE | CLFLUSH_AFTER))) { - if (flushes & CLFLUSH_BEFORE) { - clflushopt(addr); - mb(); - } + if (flushes & CLFLUSH_BEFORE) + drm_clflush_virt_range(addr, sizeof(addr));
*addr = value;
@@ -1347,7 +1345,7 @@ static void clflush_write32(u32 *addr, u32 value, unsigned int flushes) * to ensure ordering of clflush wrt to the system. */ if (flushes & CLFLUSH_AFTER) - clflushopt(addr); + drm_clflush_virt_range(addr, sizeof(addr)); } else *addr = value; }
From: kernel test robot lkp@intel.com
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:1310:32-38: ERROR: application of sizeof to pointer drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:1322:32-38: ERROR: application of sizeof to pointer
sizeof when applied to a pointer typed expression gives the size of the pointer
Generated by: scripts/coccinelle/misc/noderef.cocci
CC: Michael Cheng michael.cheng@intel.com Reported-by: kernel test robot lkp@intel.com Signed-off-by: kernel test robot lkp@intel.com ---
url: https://github.com/0day-ci/linux/commits/Michael-Cheng/Use-drm_clflush-inste... base: git://anongit.freedesktop.org/drm-intel for-linux-next :::::: branch date: 2 days ago :::::: commit date: 2 days ago
i915_gem_execbuffer.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -1307,7 +1307,7 @@ static void clflush_write32(u32 *addr, u { if (unlikely(flushes & (CLFLUSH_BEFORE | CLFLUSH_AFTER))) { if (flushes & CLFLUSH_BEFORE) - drm_clflush_virt_range(addr, sizeof(addr)); + drm_clflush_virt_range(addr, sizeof(*addr));
*addr = value;
@@ -1319,7 +1319,7 @@ static void clflush_write32(u32 *addr, u * to ensure ordering of clflush wrt to the system. */ if (flushes & CLFLUSH_AFTER) - drm_clflush_virt_range(addr, sizeof(addr)); + drm_clflush_virt_range(addr, sizeof(*addr)); } else *addr = value; }
Hi Michael,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-intel/for-linux-next] [also build test WARNING on drm-tip/drm-tip drm/drm-next v5.17-rc3] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Michael-Cheng/Use-drm_clflush-inste... base: git://anongit.freedesktop.org/drm-intel for-linux-next config: x86_64-randconfig-c002 (https://download.01.org/0day-ci/archive/20220210/202202100010.fBBNyCpm-lkp@i...) compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot lkp@intel.com
cocci warnings: (new ones prefixed by >>)
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:1310:32-38: ERROR: application of sizeof to pointer
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:1322:32-38: ERROR: application of sizeof to pointer
Please review and possibly fold the followup patch.
--- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
Replace all occurance of cache_clflush_range with drm_clflush_virt_range. This will prevent compile errors on non-x86 platforms.
Signed-off-by: Michael Cheng michael.cheng@intel.com --- drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 12 ++++++------ drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 2 +- drivers/gpu/drm/i915/gt/intel_gtt.c | 2 +- drivers/gpu/drm/i915/gt/intel_ppgtt.c | 2 +- drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +- 5 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c index c43e724afa9f..d0999e92621b 100644 --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c @@ -444,11 +444,11 @@ gen8_ppgtt_insert_pte(struct i915_ppgtt *ppgtt, pd = pdp->entry[gen8_pd_index(idx, 2)]; }
- clflush_cache_range(vaddr, PAGE_SIZE); + drm_clflush_virt_range(vaddr, PAGE_SIZE); vaddr = px_vaddr(i915_pt_entry(pd, gen8_pd_index(idx, 1))); } } while (1); - clflush_cache_range(vaddr, PAGE_SIZE); + drm_clflush_virt_range(vaddr, PAGE_SIZE);
return idx; } @@ -532,7 +532,7 @@ static void gen8_ppgtt_insert_huge(struct i915_address_space *vm, } } while (rem >= page_size && index < I915_PDES);
- clflush_cache_range(vaddr, PAGE_SIZE); + drm_clflush_virt_range(vaddr, PAGE_SIZE);
/* * Is it safe to mark the 2M block as 64K? -- Either we have @@ -548,7 +548,7 @@ static void gen8_ppgtt_insert_huge(struct i915_address_space *vm, I915_GTT_PAGE_SIZE_2M)))) { vaddr = px_vaddr(pd); vaddr[maybe_64K] |= GEN8_PDE_IPS_64K; - clflush_cache_range(vaddr, PAGE_SIZE); + drm_clflush_virt_range(vaddr, PAGE_SIZE); page_size = I915_GTT_PAGE_SIZE_64K;
/* @@ -569,7 +569,7 @@ static void gen8_ppgtt_insert_huge(struct i915_address_space *vm, for (i = 1; i < index; i += 16) memset64(vaddr + i, encode, 15);
- clflush_cache_range(vaddr, PAGE_SIZE); + drm_clflush_virt_range(vaddr, PAGE_SIZE); } }
@@ -617,7 +617,7 @@ static void gen8_ppgtt_insert_entry(struct i915_address_space *vm,
vaddr = px_vaddr(i915_pt_entry(pd, gen8_pd_index(idx, 1))); vaddr[gen8_pd_index(idx, 0)] = gen8_pte_encode(addr, level, flags); - clflush_cache_range(&vaddr[gen8_pd_index(idx, 0)], sizeof(*vaddr)); + drm_clflush_virt_range(&vaddr[gen8_pd_index(idx, 0)], sizeof(*vaddr)); }
static int gen8_init_scratch(struct i915_address_space *vm) diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c index cc561cfae808..bbe33794b34d 100644 --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c @@ -2822,7 +2822,7 @@ static void execlists_sanitize(struct intel_engine_cs *engine) sanitize_hwsp(engine);
/* And scrub the dirty cachelines for the HWSP */ - clflush_cache_range(engine->status_page.addr, PAGE_SIZE); + drm_clflush_virt_range(engine->status_page.addr, PAGE_SIZE);
intel_engine_reset_pinned_contexts(engine); } diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c index 0d6bbc8c57f2..9b594be9102f 100644 --- a/drivers/gpu/drm/i915/gt/intel_gtt.c +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c @@ -255,7 +255,7 @@ fill_page_dma(struct drm_i915_gem_object *p, const u64 val, unsigned int count) void *vaddr = __px_vaddr(p);
memset64(vaddr, val, count); - clflush_cache_range(vaddr, PAGE_SIZE); + drm_clflush_virt_range(vaddr, PAGE_SIZE); }
static void poison_scratch_page(struct drm_i915_gem_object *scratch) diff --git a/drivers/gpu/drm/i915/gt/intel_ppgtt.c b/drivers/gpu/drm/i915/gt/intel_ppgtt.c index 48e6e2f87700..bd474a5123cb 100644 --- a/drivers/gpu/drm/i915/gt/intel_ppgtt.c +++ b/drivers/gpu/drm/i915/gt/intel_ppgtt.c @@ -90,7 +90,7 @@ write_dma_entry(struct drm_i915_gem_object * const pdma, u64 * const vaddr = __px_vaddr(pdma);
vaddr[idx] = encoded_entry; - clflush_cache_range(&vaddr[idx], sizeof(u64)); + drm_clflush_virt_range(&vaddr[idx], sizeof(u64)); }
void diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c index b3a429a92c0d..89020706adc4 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c @@ -3573,7 +3573,7 @@ static void guc_sanitize(struct intel_engine_cs *engine) sanitize_hwsp(engine);
/* And scrub the dirty cachelines for the HWSP */ - clflush_cache_range(engine->status_page.addr, PAGE_SIZE); + drm_clflush_virt_range(engine->status_page.addr, PAGE_SIZE);
intel_engine_reset_pinned_contexts(engine); }
Use flush_tlb_kernel_range when invoking drm_clflush_virt_range on arm64 platforms. Using flush_tlb_kernel_range will:
1. Make sure prior page-table updates have been completed 2. Invalidate the TLB 3. Check if the TLB invalidation has been completed
Signed-off-by: Michael Cheng michael.cheng@intel.com --- drivers/gpu/drm/drm_cache.c | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c index f19d9acbe959..d2506060a7c8 100644 --- a/drivers/gpu/drm/drm_cache.c +++ b/drivers/gpu/drm/drm_cache.c @@ -176,6 +176,10 @@ drm_clflush_virt_range(void *addr, unsigned long length)
if (wbinvd_on_all_cpus()) pr_err("Timed out waiting for cache flush\n"); + +#elif defined(CONFIG_ARM64) + void *end = addr + length; + flush_tlb_kernel_range(*addr, *end); #else pr_err("Architecture has no drm_cache.c support\n"); WARN_ON_ONCE(1);
Hi Michael,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next] [also build test ERROR on drm-tip/drm-tip drm/drm-next v5.17-rc3 next-20220207] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Michael-Cheng/Use-drm_clflush-inste... base: git://anongit.freedesktop.org/drm-intel for-linux-next config: arm64-randconfig-r005-20220207 (https://download.01.org/0day-ci/archive/20220208/202202081151.wYD1tE4p-lkp@i...) compiler: clang version 15.0.0 (https://github.com/llvm/llvm-project 0d8850ae2cae85d49bea6ae0799fa41c7202c05c) reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # install arm64 cross compiling tool for clang build # apt-get install binutils-aarch64-linux-gnu # https://github.com/0day-ci/linux/commit/f2fb6ade1531d88b046e245e8b854a7422a0... git remote add linux-review https://github.com/0day-ci/linux git fetch --no-tags linux-review Michael-Cheng/Use-drm_clflush-instead-of-clflush/20220208-041326 git checkout f2fb6ade1531d88b046e245e8b854a7422a05a14 # save the config file to linux build tree mkdir build_dir COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=arm64 SHELL=/bin/bash
If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot lkp@intel.com
All errors (new ones prefixed by >>):
drivers/gpu/drm/drm_cache.c:182:25: error: passing 'void' to parameter of incompatible type 'unsigned long'
flush_tlb_kernel_range(*addr, *end); ^~~~~ arch/arm64/include/asm/tlbflush.h:374:57: note: passing argument to parameter 'start' here static inline void flush_tlb_kernel_range(unsigned long start, unsigned long end) ^ 1 error generated.
vim +182 drivers/gpu/drm/drm_cache.c
151 152 /** 153 * drm_clflush_virt_range - Flush dcache lines of a region 154 * @addr: Initial kernel memory address. 155 * @length: Region size. 156 * 157 * Flush every data cache line entry that points to an address in the 158 * region requested. 159 */ 160 void 161 drm_clflush_virt_range(void *addr, unsigned long length) 162 { 163 #if defined(CONFIG_X86) 164 if (static_cpu_has(X86_FEATURE_CLFLUSH)) { 165 const int size = boot_cpu_data.x86_clflush_size; 166 void *end = addr + length; 167 168 addr = (void *)(((unsigned long)addr) & -size); 169 mb(); /*CLFLUSH is only ordered with a full memory barrier*/ 170 for (; addr < end; addr += size) 171 clflushopt(addr); 172 clflushopt(end - 1); /* force serialisation */ 173 mb(); /*Ensure that every data cache line entry is flushed*/ 174 return; 175 } 176 177 if (wbinvd_on_all_cpus()) 178 pr_err("Timed out waiting for cache flush\n"); 179 180 #elif defined(CONFIG_ARM64) 181 void *end = addr + length;
182 flush_tlb_kernel_range(*addr, *end);
183 #else 184 pr_err("Architecture has no drm_cache.c support\n"); 185 WARN_ON_ONCE(1); 186 #endif 187 } 188 EXPORT_SYMBOL(drm_clflush_virt_range); 189
--- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
Hi Michael,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next] [also build test ERROR on drm-tip/drm-tip drm/drm-next v5.17-rc3 next-20220207] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Michael-Cheng/Use-drm_clflush-inste... base: git://anongit.freedesktop.org/drm-intel for-linux-next config: arm64-defconfig (https://download.01.org/0day-ci/archive/20220208/202202081258.VY7Y7JnA-lkp@i...) compiler: aarch64-linux-gcc (GCC) 11.2.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # https://github.com/0day-ci/linux/commit/f2fb6ade1531d88b046e245e8b854a7422a0... git remote add linux-review https://github.com/0day-ci/linux git fetch --no-tags linux-review Michael-Cheng/Use-drm_clflush-instead-of-clflush/20220208-041326 git checkout f2fb6ade1531d88b046e245e8b854a7422a05a14 # save the config file to linux build tree mkdir build_dir COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross O=build_dir ARCH=arm64 SHELL=/bin/bash drivers/gpu/drm/
If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot lkp@intel.com
All error/warnings (new ones prefixed by >>):
drivers/gpu/drm/drm_cache.c: In function 'drm_clflush_virt_range':
drivers/gpu/drm/drm_cache.c:182:32: warning: dereferencing 'void *' pointer
182 | flush_tlb_kernel_range(*addr, *end); | ^~~~~ drivers/gpu/drm/drm_cache.c:182:39: warning: dereferencing 'void *' pointer 182 | flush_tlb_kernel_range(*addr, *end); | ^~~~
drivers/gpu/drm/drm_cache.c:182:32: error: invalid use of void expression
182 | flush_tlb_kernel_range(*addr, *end); | ^~~~~ drivers/gpu/drm/drm_cache.c:182:39: error: invalid use of void expression 182 | flush_tlb_kernel_range(*addr, *end); | ^~~~
vim +182 drivers/gpu/drm/drm_cache.c
151 152 /** 153 * drm_clflush_virt_range - Flush dcache lines of a region 154 * @addr: Initial kernel memory address. 155 * @length: Region size. 156 * 157 * Flush every data cache line entry that points to an address in the 158 * region requested. 159 */ 160 void 161 drm_clflush_virt_range(void *addr, unsigned long length) 162 { 163 #if defined(CONFIG_X86) 164 if (static_cpu_has(X86_FEATURE_CLFLUSH)) { 165 const int size = boot_cpu_data.x86_clflush_size; 166 void *end = addr + length; 167 168 addr = (void *)(((unsigned long)addr) & -size); 169 mb(); /*CLFLUSH is only ordered with a full memory barrier*/ 170 for (; addr < end; addr += size) 171 clflushopt(addr); 172 clflushopt(end - 1); /* force serialisation */ 173 mb(); /*Ensure that every data cache line entry is flushed*/ 174 return; 175 } 176 177 if (wbinvd_on_all_cpus()) 178 pr_err("Timed out waiting for cache flush\n"); 179 180 #elif defined(CONFIG_ARM64) 181 void *end = addr + length;
182 flush_tlb_kernel_range(*addr, *end);
183 #else 184 pr_err("Architecture has no drm_cache.c support\n"); 185 WARN_ON_ONCE(1); 186 #endif 187 } 188 EXPORT_SYMBOL(drm_clflush_virt_range); 189
--- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
On 07/02/2022 20:11, Michael Cheng wrote:
Use flush_tlb_kernel_range when invoking drm_clflush_virt_range on arm64 platforms. Using flush_tlb_kernel_range will:
- Make sure prior page-table updates have been completed
- Invalidate the TLB
- Check if the TLB invalidation has been completed
Arm does not have a clflush equivalent but invalidating TLBs there includes flushing caches?
Regards,
Tvrtko
Signed-off-by: Michael Cheng michael.cheng@intel.com
drivers/gpu/drm/drm_cache.c | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c index f19d9acbe959..d2506060a7c8 100644 --- a/drivers/gpu/drm/drm_cache.c +++ b/drivers/gpu/drm/drm_cache.c @@ -176,6 +176,10 @@ drm_clflush_virt_range(void *addr, unsigned long length)
if (wbinvd_on_all_cpus()) pr_err("Timed out waiting for cache flush\n");
+#elif defined(CONFIG_ARM64)
- void *end = addr + length;
- flush_tlb_kernel_range(*addr, *end); #else pr_err("Architecture has no drm_cache.c support\n"); WARN_ON_ONCE(1);
Ah, thanks for asking this question. It seems like I was not thinking correctly. We are trying to flush dcache lines within this function and not the tlb.
On 2022-02-08 2:20 a.m., Tvrtko Ursulin wrote:
On 07/02/2022 20:11, Michael Cheng wrote:
Use flush_tlb_kernel_range when invoking drm_clflush_virt_range on arm64 platforms. Using flush_tlb_kernel_range will:
- Make sure prior page-table updates have been completed
- Invalidate the TLB
- Check if the TLB invalidation has been completed
Arm does not have a clflush equivalent but invalidating TLBs there includes flushing caches?
Regards,
Tvrtko
Signed-off-by: Michael Cheng michael.cheng@intel.com
drivers/gpu/drm/drm_cache.c | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c index f19d9acbe959..d2506060a7c8 100644 --- a/drivers/gpu/drm/drm_cache.c +++ b/drivers/gpu/drm/drm_cache.c @@ -176,6 +176,10 @@ drm_clflush_virt_range(void *addr, unsigned long length) if (wbinvd_on_all_cpus()) pr_err("Timed out waiting for cache flush\n");
+#elif defined(CONFIG_ARM64) + void *end = addr + length; + flush_tlb_kernel_range(*addr, *end); #else pr_err("Architecture has no drm_cache.c support\n"); WARN_ON_ONCE(1);
dri-devel@lists.freedesktop.org
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kernel test robot -
Michael Cheng -
Tvrtko Ursulin