On Thu, 2020-12-10 at 23:40 +0800, Chun-Kuang Hu wrote:

Hi, Yongqiang:

Yongqiang Niu yongqiang.niu@mediatek.com 於 2020年12月10日 週四 下午5:22寫道：

...

rdma fifo size may be different even in same SOC, add this property to the corresponding rdma

Signed-off-by: Yongqiang Niu yongqiang.niu@mediatek.com

.../bindings/display/mediatek/mediatek,disp.txt | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt index 1212207..64c64ee 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt @@ -66,6 +66,13 @@ Required properties (DMA function blocks): argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt for details.

+Optional properties (RDMA function blocks): +- mediatek,rdma_fifo_size: rdma fifo size may be different even in same SOC, add this

• property to the corresponding rdma
• the value is the Max value which defined in hardware data sheet.
• rdma_fifo_size of rdma0 in mt8183 is 5120
• rdma_fifo_size of rdma1 in mt8183 is 2048

Examples:

mmsys: clock-controller@14000000 { @@ -207,3 +214,12 @@ od@14023000 { power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_OD>; };

+rdma1: rdma@1400c000 {

•   compatible = "mediatek,mt8183-disp-rdma";
  

•   reg = <0 0x1400c000 0 0x1000>;
  

•   interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
  

•   power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
  

•   clocks = <&mmsys CLK_MM_DISP_RDMA1>;
  

•   mediatek,rdma_fifo_size = <2048>;
  

+};

In [1], Rob has suggest that not add example of rdma1, it's better to add mediatek,rdma_fifo_size in rdma0 for example.

[1] https://patchwork.kernel.org/project/linux-mediatek/patch/1596855231-5782-2-...

Regards, Chun-Kuang.

the description of rdma0 is mt8173, and mt8173 rdma driver set the correspond fifo size already ok like this: static const struct mtk_disp_rdma_data mt8173_rdma_driver_data = { .fifo_size = SZ_8K, };

please double confirm shall we add this information into rdma0 description.

...

-- 1.8.1.1.dirty _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek

On Thu, Dec 10, 2020 at 05:07:37PM +0800, Yongqiang Niu wrote:

rdma fifo size may be different even in same SOC, add this property to the corresponding rdma

Signed-off-by: Yongqiang Niu yongqiang.niu@mediatek.com

.../bindings/display/mediatek/mediatek,disp.txt | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt index 1212207..64c64ee 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt @@ -66,6 +66,13 @@ Required properties (DMA function blocks): argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt for details.

+Optional properties (RDMA function blocks): +- mediatek,rdma_fifo_size: rdma fifo size may be different even in same SOC, add this

mediatek,rdma-fifo-size

• property to the corresponding rdma
• the value is the Max value which defined in hardware data sheet.
• rdma_fifo_size of rdma0 in mt8183 is 5120
• rdma_fifo_size of rdma1 in mt8183 is 2048

Examples:

mmsys: clock-controller@14000000 { @@ -207,3 +214,12 @@ od@14023000 { power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_OD>; };

+rdma1: rdma@1400c000 {

• compatible = "mediatek,mt8183-disp-rdma";
• reg = <0 0x1400c000 0 0x1000>;
• interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
• power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
• clocks = <&mmsys CLK_MM_DISP_RDMA1>;
• mediatek,rdma_fifo_size = <2048>;

+};

1.8.1.1.dirty

Hi, Yongqiang:

Yongqiang Niu yongqiang.niu@mediatek.com 於 2020年12月10日 週四 下午5:22寫道：

add description for mt8183 display

Reviewed-by: Chun-Kuang Hu chunkuang.hu@kernel.org

Signed-off-by: Yongqiang Niu yongqiang.niu@mediatek.com

Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt index 64c64ee..5ca693a 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt @@ -43,7 +43,7 @@ Required properties (all function blocks): "mediatek,<chip>-dpi" - DPI controller, see mediatek,dpi.txt "mediatek,<chip>-disp-mutex" - display mutex "mediatek,<chip>-disp-od" - overdrive

• the supported chips are mt2701, mt7623, mt2712 and mt8173.

• the supported chips are mt2701, mt7623, mt2712, mt8173 and mt8183.

• reg: Physical base address and length of the function block register space
• interrupts: The interrupt signal from the function block (required, except for merge and split function blocks).

-- 1.8.1.1.dirty _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek

Hi, Yongqiang:

Yongqiang Niu yongqiang.niu@mediatek.com 於 2020年12月10日 週四 下午5:08寫道：

This patch add RDMA fifo size error handle rdma fifo size will not always bigger than the calculated threshold if that case happened, we need set fifo size as the threshold

Signed-off-by: Yongqiang Niu yongqiang.niu@mediatek.com

drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 4 ++++ 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c index 794acc5..0508392 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c @@ -151,6 +151,10 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width, * account for blanking, and with a pixel depth of 4 bytes: */ threshold = width * height * vrefresh * 4 * 7 / 1000000;

•   if (threshold > rdma_fifo_size)
  

•           threshold = rdma_fifo_size;
  

If the formula is not correct, you should fix the formula not work around.

Regards, Chun-Kuang.

•   reg = RDMA_FIFO_UNDERFLOW_EN |
          RDMA_FIFO_PSEUDO_SIZE(rdma_fifo_size) |
          RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold);
  

-- 1.8.1.1.dirty _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek

Hi, Yongqiang:

Yongqiang Niu yongqiang.niu@mediatek.com 於 2020年12月11日 週五 上午8:45寫道：

On Thu, 2020-12-10 at 23:50 +0800, Chun-Kuang Hu wrote:

...

Hi, Yongqiang:

Yongqiang Niu yongqiang.niu@mediatek.com 於 2020年12月10日 週四 下午5:08寫道：

...

This patch add RDMA fifo size error handle rdma fifo size will not always bigger than the calculated threshold if that case happened, we need set fifo size as the threshold

Signed-off-by: Yongqiang Niu yongqiang.niu@mediatek.com

drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 4 ++++ 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c index 794acc5..0508392 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c @@ -151,6 +151,10 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width, * account for blanking, and with a pixel depth of 4 bytes: */ threshold = width * height * vrefresh * 4 * 7 / 1000000;

•   if (threshold > rdma_fifo_size)
  

•           threshold = rdma_fifo_size;
  

If the formula is not correct, you should fix the formula not work around.

Regards, Chun-Kuang.

how about this: threshold = max(width * height * vrefresh * 4 * 7 / 1000000, rdma_fifo_size);

When I use width = 1920, height = 1080, vrefresh = 60 to calculate, I get threshold = 2985. So I think set threshold to half of fifo size is OK for MAX_WIDTH, MAX_HEIGHT, MAX_VREFRESH (these three may be different in each SoC)

threshold = RDMA_FIFO_PSEUDO_SIZE(rdma_fifo_size) / 2;

But I worry half fifo size is too big for small resolution and let small resolution too easy to trigger burst read DRAM. So let the formula to be this:

threshold = RDMA_FIFO_PSEUDO_SIZE(rdma_fifo_size) * width * height * vrefresh / 2 / MAX_WIDTH / MAX_HEIGHT / MAX_VREFRESH;

How do you think about this?

Regards, Chun-Kuang.

...

...

•   reg = RDMA_FIFO_UNDERFLOW_EN |
          RDMA_FIFO_PSEUDO_SIZE(rdma_fifo_size) |
          RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold);
  

-- 1.8.1.1.dirty _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek

Hi, Yongqiang:

Yongqiang Niu yongqiang.niu@mediatek.com 於 2021年1月5日 週二 下午2:36寫道：

On Mon, 2020-12-14 at 22:54 +0800, Chun-Kuang Hu wrote:

...

Hi, Yongqiang:

Yongqiang Niu yongqiang.niu@mediatek.com 於 2020年12月11日 週五 上午8:45寫道：

...

On Thu, 2020-12-10 at 23:50 +0800, Chun-Kuang Hu wrote:

...

Hi, Yongqiang:

Yongqiang Niu yongqiang.niu@mediatek.com 於 2020年12月10日 週四 下午5:08寫道：

...

This patch add RDMA fifo size error handle rdma fifo size will not always bigger than the calculated threshold if that case happened, we need set fifo size as the threshold

Signed-off-by: Yongqiang Niu yongqiang.niu@mediatek.com

drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 4 ++++ 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c index 794acc5..0508392 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c @@ -151,6 +151,10 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width, * account for blanking, and with a pixel depth of 4 bytes: */ threshold = width * height * vrefresh * 4 * 7 / 1000000;

•   if (threshold > rdma_fifo_size)
  

•           threshold = rdma_fifo_size;
  

If the formula is not correct, you should fix the formula not work around.

Regards, Chun-Kuang.

how about this: threshold = max(width * height * vrefresh * 4 * 7 / 1000000, rdma_fifo_size);

When I use width = 1920, height = 1080, vrefresh = 60 to calculate, I get threshold = 2985. So I think set threshold to half of fifo size is OK for MAX_WIDTH, MAX_HEIGHT, MAX_VREFRESH (these three may be different in each SoC)

threshold = RDMA_FIFO_PSEUDO_SIZE(rdma_fifo_size) / 2;

But I worry half fifo size is too big for small resolution and let small resolution too easy to trigger burst read DRAM. So let the formula to be this:

threshold = RDMA_FIFO_PSEUDO_SIZE(rdma_fifo_size) * width * height * vrefresh / 2 / MAX_WIDTH / MAX_HEIGHT / MAX_VREFRESH;

How do you think about this?

Regards, Chun-Kuang.

how about remove this formula, and set threshold = rdma_fifo_size

This means that RDMA would always trigger burst read. In normal case, I think no hardware would trigger burst read. Only the emergency occur, the hardware trigger burst read. RDMA always triggering burst read is good for RDMA, but it may hurt other hardware to read DRAM. So I think RDMA should trigger burst read only when fifo data is under a emergency threshold.

Regards, Chun-Kuang.

...

...

...

...

•   reg = RDMA_FIFO_UNDERFLOW_EN |
          RDMA_FIFO_PSEUDO_SIZE(rdma_fifo_size) |
          RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold);
  

-- 1.8.1.1.dirty _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek

On Thu, Dec 10, 2020 at 9:07 AM Yongqiang Niu yongqiang.niu@mediatek.com wrote:

This patch add support for mediatek SOC MT8183

1. add ovl private data
2. add rdma private data
3. add mutes private data
4. add main and external path module for crtc create

Signed-off-by: Yongqiang Niu yongqiang.niu@mediatek.com

drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 18 ++++++++++++ drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 ++++ drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 47 ++++++++++++++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_drm_drv.c | 43 +++++++++++++++++++++++++++++ 4 files changed, 114 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c index 28651bc..8cf9f3b 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -430,11 +430,29 @@ static int mtk_disp_ovl_remove(struct platform_device *pdev) .fmt_rgb565_is_0 = true, };

+static const struct mtk_disp_ovl_data mt8183_ovl_driver_data = {

•   .addr = DISP_REG_OVL_ADDR_MT8173,
  

•   .gmc_bits = 10,
  

•   .layer_nr = 4,
  

•   .fmt_rgb565_is_0 = true,
  

+};

+static const struct mtk_disp_ovl_data mt8183_ovl_2l_driver_data = {

•   .addr = DISP_REG_OVL_ADDR_MT8173,
  

•   .gmc_bits = 10,
  

•   .layer_nr = 2,
  

•   .fmt_rgb565_is_0 = true,
  

+};

static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = { { .compatible = "mediatek,mt2701-disp-ovl", .data = &mt2701_ovl_driver_data}, { .compatible = "mediatek,mt8173-disp-ovl", .data = &mt8173_ovl_driver_data},

•   { .compatible = "mediatek,mt8183-disp-ovl",
  

•     .data = &mt8183_ovl_driver_data},
  

•   { .compatible = "mediatek,mt8183-disp-ovl-2l",
  

•     .data = &mt8183_ovl_2l_driver_data},
    {},
  

}; MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c index 0508392..86e77c2 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c @@ -359,11 +359,17 @@ static int mtk_disp_rdma_remove(struct platform_device *pdev) .fifo_size = SZ_8K, };

+static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = {

•   .fifo_size = 5 * SZ_1K,
  

+};

static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = { { .compatible = "mediatek,mt2701-disp-rdma", .data = &mt2701_rdma_driver_data}, { .compatible = "mediatek,mt8173-disp-rdma", .data = &mt8173_rdma_driver_data},

•   { .compatible = "mediatek,mt8183-disp-rdma",
  

•     .data = &mt8183_rdma_driver_data},
    {},
  

}; MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match); diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c index 014c1bb..60788c1 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c @@ -15,6 +15,8 @@

#define MT2701_DISP_MUTEX0_MOD0 0x2c #define MT2701_DISP_MUTEX0_SOF0 0x30 +#define MT8183_DISP_MUTEX0_MOD0 0x30 +#define MT8183_DISP_MUTEX0_SOF0 0x2c

#define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) @@ -25,6 +27,18 @@

#define INT_MUTEX BIT(1)

+#define MT8183_MUTEX_MOD_DISP_RDMA0 0 +#define MT8183_MUTEX_MOD_DISP_RDMA1 1 +#define MT8183_MUTEX_MOD_DISP_OVL0 9 +#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10 +#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11 +#define MT8183_MUTEX_MOD_DISP_WDMA0 12 +#define MT8183_MUTEX_MOD_DISP_COLOR0 13 +#define MT8183_MUTEX_MOD_DISP_CCORR0 14 +#define MT8183_MUTEX_MOD_DISP_AAL0 15 +#define MT8183_MUTEX_MOD_DISP_GAMMA0 16 +#define MT8183_MUTEX_MOD_DISP_DITHER0 17

#define MT8173_MUTEX_MOD_DISP_OVL0 11 #define MT8173_MUTEX_MOD_DISP_OVL1 12 #define MT8173_MUTEX_MOD_DISP_RDMA0 13 @@ -74,6 +88,10 @@ #define MUTEX_SOF_DSI2 5 #define MUTEX_SOF_DSI3 6

+#define MT8183_MUTEX_SOF_DPI0 2 +#define MT8183_MUTEX_EOF_DSI0 (MUTEX_SOF_DSI0 << 6) +#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6)

struct mtk_disp_mutex { int id; @@ -153,6 +171,20 @@ struct mtk_ddp { [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1, };

+static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {

•   [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0,
  

•   [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0,
  

•   [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0,
  

•   [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0,
  

•   [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0,
  

•   [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0,
  

•   [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L,
  

•   [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L,
  

•   [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0,
  

•   [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1,
  

•   [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
  

+};

static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, @@ -163,6 +195,12 @@ struct mtk_ddp { [DDP_MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3, };

+static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = {

•   [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
  

•   [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0,
  

•   [DDP_MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0,
  

+};

static const struct mtk_ddp_data mt2701_ddp_driver_data = { .mutex_mod = mt2701_mutex_mod, .mutex_sof = mt2712_mutex_sof, @@ -184,6 +222,13 @@ struct mtk_ddp { .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0, };

+static const struct mtk_ddp_data mt8183_ddp_driver_data = {

•   .mutex_mod = mt8183_mutex_mod,
  

•   .mutex_sof = mt8183_mutex_sof,
  

•   .mutex_mod_reg = MT8183_DISP_MUTEX0_MOD0,
  

•   .mutex_sof_reg = MT8183_DISP_MUTEX0_SOF0,
  

Tested on an mt8183 device, and get:

[ 10.014978] mediatek-ddp 14016000.mutex: Failed to get clock [ 10.026441] mediatek-ddp: probe of 14016000.mutex failed with error -2

Since mt8183 mutex doesn't need clock, I think this should add .no_clk = true,

+};

struct mtk_disp_mutex *mtk_disp_mutex_get(struct device *dev, unsigned int id) { struct mtk_ddp *ddp = dev_get_drvdata(dev); @@ -402,6 +447,8 @@ static int mtk_ddp_remove(struct platform_device *pdev) .data = &mt2712_ddp_driver_data}, { .compatible = "mediatek,mt8173-disp-mutex", .data = &mt8173_ddp_driver_data},

•   { .compatible = "mediatek,mt8183-disp-mutex",
  

•     .data = &mt8183_ddp_driver_data},
    {},
  

}; MODULE_DEVICE_TABLE(of, ddp_driver_dt_match); diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index 59c85c6..a7e9f88 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -131,6 +131,24 @@ DDP_COMPONENT_DPI0, };

+static const enum mtk_ddp_comp_id mt8183_mtk_ddp_main[] = {

•   DDP_COMPONENT_OVL0,
  

•   DDP_COMPONENT_OVL_2L0,
  

•   DDP_COMPONENT_RDMA0,
  

•   DDP_COMPONENT_COLOR0,
  

•   DDP_COMPONENT_CCORR,
  

•   DDP_COMPONENT_AAL0,
  

•   DDP_COMPONENT_GAMMA,
  

•   DDP_COMPONENT_DITHER,
  

•   DDP_COMPONENT_DSI0,
  

+};

+static const enum mtk_ddp_comp_id mt8183_mtk_ddp_ext[] = {

•   DDP_COMPONENT_OVL_2L1,
  

•   DDP_COMPONENT_RDMA1,
  

•   DDP_COMPONENT_DPI0,
  

+};

static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { .main_path = mt2701_mtk_ddp_main, .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main), @@ -163,6 +181,13 @@ .ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext), };

+static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {

•   .main_path = mt8183_mtk_ddp_main,
  

•   .main_len = ARRAY_SIZE(mt8183_mtk_ddp_main),
  

•   .ext_path = mt8183_mtk_ddp_ext,
  

•   .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
  

+};

static int mtk_drm_kms_init(struct drm_device *drm) { struct mtk_drm_private *private = drm->dev_private; @@ -403,12 +428,20 @@ static void mtk_drm_unbind(struct device *dev) .data = (void *)MTK_DISP_OVL }, { .compatible = "mediatek,mt8173-disp-ovl", .data = (void *)MTK_DISP_OVL },

•   { .compatible = "mediatek,mt8183-disp-ovl",
  

•     .data = (void *)MTK_DISP_OVL },
  

•   { .compatible = "mediatek,mt8183-disp-ovl-2l",
  

•     .data = (void *)MTK_DISP_OVL_2L },
    { .compatible = "mediatek,mt2701-disp-rdma",
      .data = (void *)MTK_DISP_RDMA },
    { .compatible = "mediatek,mt8173-disp-rdma",
      .data = (void *)MTK_DISP_RDMA },
  

•   { .compatible = "mediatek,mt8183-disp-rdma",
  

•     .data = (void *)MTK_DISP_RDMA },
    { .compatible = "mediatek,mt8173-disp-wdma",
      .data = (void *)MTK_DISP_WDMA },
  

•   { .compatible = "mediatek,mt8183-disp-ccorr",
  

•     .data = (void *)MTK_DISP_CCORR },
    { .compatible = "mediatek,mt2701-disp-color",
      .data = (void *)MTK_DISP_COLOR },
    { .compatible = "mediatek,mt8173-disp-color",
  

@@ -417,22 +450,30 @@ static void mtk_drm_unbind(struct device *dev) .data = (void *)MTK_DISP_AAL}, { .compatible = "mediatek,mt8173-disp-gamma", .data = (void *)MTK_DISP_GAMMA, },

•   { .compatible = "mediatek,mt8183-disp-dither",
  

•     .data = (void *)MTK_DISP_DITHER },
    { .compatible = "mediatek,mt8173-disp-ufoe",
      .data = (void *)MTK_DISP_UFOE },
    { .compatible = "mediatek,mt2701-dsi",
      .data = (void *)MTK_DSI },
    { .compatible = "mediatek,mt8173-dsi",
      .data = (void *)MTK_DSI },
  

•   { .compatible = "mediatek,mt8183-dsi",
  

•     .data = (void *)MTK_DSI },
    { .compatible = "mediatek,mt2701-dpi",
      .data = (void *)MTK_DPI },
    { .compatible = "mediatek,mt8173-dpi",
      .data = (void *)MTK_DPI },
  

•   { .compatible = "mediatek,mt8183-dpi",
  

•     .data = (void *)MTK_DPI },
    { .compatible = "mediatek,mt2701-disp-mutex",
      .data = (void *)MTK_DISP_MUTEX },
    { .compatible = "mediatek,mt2712-disp-mutex",
      .data = (void *)MTK_DISP_MUTEX },
    { .compatible = "mediatek,mt8173-disp-mutex",
      .data = (void *)MTK_DISP_MUTEX },
  

•   { .compatible = "mediatek,mt8183-disp-mutex",
  

•     .data = (void *)MTK_DISP_MUTEX },
    { .compatible = "mediatek,mt2701-disp-pwm",
      .data = (void *)MTK_DISP_BLS },
    { .compatible = "mediatek,mt8173-disp-pwm",
  

@@ -451,6 +492,8 @@ static void mtk_drm_unbind(struct device *dev) .data = &mt2712_mmsys_driver_data}, { .compatible = "mediatek,mt8173-mmsys", .data = &mt8173_mmsys_driver_data},

•   { .compatible = "mediatek,mt8183-mmsys",
  

•     .data = &mt8183_mmsys_driver_data},
    { }
  

};