RZ/G2L SoC embeds Mali-G31 bifrost GPU. This patch series aims to add support for the same
It is tested with latest drm-misc-next + mesa 21.3.0 + out of tree patch for (du + DSI) + platform specific mesa configuration for RZ/G2L.
Tested the kmscube application.
test logs:- root@smarc-rzg2l:~# kmscube Using display 0xaaaadb6e7d30 with EGL version 1.4 =================================== EGL information: version: "1.4" vendor: "Mesa Project" ..... =================================== OpenGL ES 2.x information: version: "OpenGL ES 3.1 Mesa 21.3.0" shading language version: "OpenGL ES GLSL ES 3.10" vendor: "Panfrost" renderer: "Mali-G31 (Panfrost)" .... =================================== ^C
root@smarc-rzg2l:~# cat /proc/interrupts | grep panfrost 82: 587287 0 GICv3 186 Level panfrost-job 83: 2 0 GICv3 187 Level panfrost-mmu 84: 8 0 GICv3 185 Level panfrost-gpu
root@smarc-rzg2l:~# cat /sys/class/devfreq/11840000.gpu/trans_stat From : To : 50000000 62500000 100000000 125000000 200000000 250000000 400000000 500000000 time(ms) * 50000000: 0 0 0 0 0 0 0 0 72 62500000: 0 0 0 0 0 0 0 0 0 100000000: 0 0 0 0 0 0 0 0 0 125000000: 0 0 0 0 0 0 0 1 68 200000000: 0 0 0 0 0 0 0 1 68 250000000: 1 0 0 0 0 0 0 0 84 400000000: 0 0 0 0 0 0 0 0 0 500000000: 0 0 0 1 1 1 0 0 736 Total transition : 6 root@smarc-rzg2l:~# kmscube Using display 0xaaaaf7a421b0 with EGL version 1.4 =================================== EGL information: version: "1.4" vendor: "Mesa Project" ..... =================================== OpenGL ES 2.x information: version: "OpenGL ES 3.1 Mesa 21.3.0" shading language version: "OpenGL ES GLSL ES 3.10" vendor: "Panfrost" renderer: "Mali-G31 (Panfrost)" ...... ===================================
root@smarc-rzg2l:~# root@smarc-rzg2l:~# root@smarc-rzg2l:~# cat /sys/class/devfreq/11840000.gpu/trans_stat From : To : 50000000 62500000 100000000 125000000 200000000 250000000 400000000 500000000 time(ms) * 50000000: 0 0 0 0 0 0 0 1 144 62500000: 0 0 0 0 0 0 0 0 0 100000000: 0 0 0 0 0 0 0 9 524 125000000: 0 0 9 0 0 0 0 3 2544 200000000: 0 0 0 11 0 0 0 46 3304 250000000: 1 0 0 0 33 0 0 0 7496 400000000: 0 0 0 0 16 19 0 0 2024 500000000: 1 0 0 1 8 15 35 0 4032 Total transition : 208
Platform specific mesa configuration patch for RZ/G2L --------------------- src/gallium/targets/dri/meson.build + 'rcar-du_dri.so', src/gallium/targets/dri/target.c +DEFINE_LOADER_DRM_ENTRYPOINT(rcar_du)
V2->V3: * Moved optional clock-names and reset-names to SoC-specific conditional schemas. * minimum number of reset for the generic GPU is set to 1. * Documented number of clocks, resets, interrupts and interrupt-names in RZ/G2L SoC-specific conditional schemas. * Updated commit description for patch#3 V1->V2: * Removed clock patches from this seies, as it is accepted for 5.17 * Added Rb tag from Geert * Added reset-names required property for RZ/G2L and updated the board dtsi.
Biju Das (3): dt-bindings: gpu: mali-bifrost: Document RZ/G2L support arm64: dts: renesas: r9a07g044: Add Mali-G31 GPU node arm64: dts: renesas: rzg2l-smarc-som: Add vdd core regulator
.../bindings/gpu/arm,mali-bifrost.yaml | 45 ++++++++++++- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 65 +++++++++++++++++++ .../boot/dts/renesas/rzg2l-smarc-som.dtsi | 13 ++++ 3 files changed, 121 insertions(+), 2 deletions(-)
The Renesas RZ/G2{L, LC} SoC (a.k.a R9A07G044) has a Bifrost Mali-G31 GPU, add a compatible string for it.
Signed-off-by: Biju Das biju.das.jz@bp.renesas.com Reviewed-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com --- v2->v3: * Moved optional clock-names and reset-names to SoC-specific conditional schemas. * minimum number of reset for the generic GPU is set to 1. * Documented number of clocks, resets, interrupts and interrupt-names in RZ/G2L SoC-specific conditional schemas. v1->v2: * Updated minItems for resets as 2 * Documented optional property reset-names * Documented reset-names as required property for RZ/G2L SoC. --- .../bindings/gpu/arm,mali-bifrost.yaml | 45 ++++++++++++++++++- 1 file changed, 43 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml index 6f98dd55fb4c..63a08f3f321d 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml +++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml @@ -19,6 +19,7 @@ properties: - amlogic,meson-g12a-mali - mediatek,mt8183-mali - realtek,rtd1619-mali + - renesas,r9a07g044-mali - rockchip,px30-mali - rockchip,rk3568-mali - const: arm,mali-bifrost # Mali Bifrost GPU model/revision is fully discoverable @@ -27,19 +28,26 @@ properties: maxItems: 1
interrupts: + minItems: 3 items: - description: Job interrupt - description: MMU interrupt - description: GPU interrupt + - description: Event interrupt
interrupt-names: + minItems: 3 items: - const: job - const: mmu - const: gpu + - const: event
clocks: - maxItems: 1 + minItems: 1 + maxItems: 3 + + clock-names: true
mali-supply: true
@@ -52,7 +60,10 @@ properties: maxItems: 3
resets: - maxItems: 2 + minItems: 1 + maxItems: 3 + + reset-names: true
"#cooling-cells": const: 2 @@ -94,6 +105,36 @@ allOf: then: required: - resets + - if: + properties: + compatible: + contains: + const: renesas,r9a07g044-mali + then: + properties: + interrupts: + minItems: 4 + interrupt-names: + minItems: 4 + clocks: + minItems: 3 + clock-names: + items: + - const: gpu + - const: bus + - const: bus_ace + resets: + minItems: 3 + reset-names: + items: + - const: rst + - const: axi_rst + - const: ace_rst + required: + - clock-names + - power-domains + - resets + - reset-names - if: properties: compatible:
Hi All,
Gentle ping.
Cheers, Biju
Subject: [PATCH v3 1/3] dt-bindings: gpu: mali-bifrost: Document RZ/G2L support
The Renesas RZ/G2{L, LC} SoC (a.k.a R9A07G044) has a Bifrost Mali-G31 GPU, add a compatible string for it.
Signed-off-by: Biju Das biju.das.jz@bp.renesas.com Reviewed-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com
v2->v3:
- Moved optional clock-names and reset-names to SoC-specific conditional
schemas.
- minimum number of reset for the generic GPU is set to 1.
- Documented number of clocks, resets, interrupts and interrupt-names in
RZ/G2L SoC-specific conditional schemas. v1->v2:
- Updated minItems for resets as 2
- Documented optional property reset-names
- Documented reset-names as required property for RZ/G2L SoC.
.../bindings/gpu/arm,mali-bifrost.yaml | 45 ++++++++++++++++++- 1 file changed, 43 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml index 6f98dd55fb4c..63a08f3f321d 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml +++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml @@ -19,6 +19,7 @@ properties: - amlogic,meson-g12a-mali - mediatek,mt8183-mali - realtek,rtd1619-mali
- renesas,r9a07g044-mali - rockchip,px30-mali - rockchip,rk3568-mali - const: arm,mali-bifrost # Mali Bifrost GPU model/revision isfully discoverable @@ -27,19 +28,26 @@ properties: maxItems: 1
interrupts:
minItems: 3 items:
- description: Job interrupt
- description: MMU interrupt
- description: GPU interrupt
- description: Event interruptinterrupt-names:
minItems: 3 items:
- const: job
- const: mmu
- const: gpu
- const: eventclocks:
- maxItems: 1
minItems: 1
maxItems: 3
clock-names: true
mali-supply: true
@@ -52,7 +60,10 @@ properties: maxItems: 3
resets:
- maxItems: 2
minItems: 1
maxItems: 3
reset-names: true
"#cooling-cells": const: 2
@@ -94,6 +105,36 @@ allOf: then: required: - resets
- if:
properties:compatible:contains:const: renesas,r9a07g044-mali- then:
properties:interrupts:minItems: 4interrupt-names:minItems: 4clocks:minItems: 3clock-names:items:- const: gpu- const: bus- const: bus_aceresets:minItems: 3reset-names:items:- const: rst- const: axi_rst- const: ace_rstrequired:- clock-names- power-domains- resets- reset-names
- if: properties: compatible:
-- 2.17.1
On Fri, Dec 10, 2021 at 02:44:06PM +0000, Biju Das wrote:
Hi All,
Gentle ping.
2 days later is not a gentle ping. If you want to check status, go look at PW[1]. If it is in there, it's in my queue (only about 100 patches ATM).
Rob
[1] https://patchwork.ozlabs.org/project/devicetree-bindings/list/
Cheers, Biju
Subject: [PATCH v3 1/3] dt-bindings: gpu: mali-bifrost: Document RZ/G2L support
The Renesas RZ/G2{L, LC} SoC (a.k.a R9A07G044) has a Bifrost Mali-G31 GPU, add a compatible string for it.
Signed-off-by: Biju Das biju.das.jz@bp.renesas.com Reviewed-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com
v2->v3:
- Moved optional clock-names and reset-names to SoC-specific conditional
schemas.
- minimum number of reset for the generic GPU is set to 1.
- Documented number of clocks, resets, interrupts and interrupt-names in
RZ/G2L SoC-specific conditional schemas. v1->v2:
- Updated minItems for resets as 2
- Documented optional property reset-names
- Documented reset-names as required property for RZ/G2L SoC.
.../bindings/gpu/arm,mali-bifrost.yaml | 45 ++++++++++++++++++- 1 file changed, 43 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml index 6f98dd55fb4c..63a08f3f321d 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml +++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml @@ -19,6 +19,7 @@ properties: - amlogic,meson-g12a-mali - mediatek,mt8183-mali - realtek,rtd1619-mali
- renesas,r9a07g044-mali - rockchip,px30-mali - rockchip,rk3568-mali - const: arm,mali-bifrost # Mali Bifrost GPU model/revision isfully discoverable @@ -27,19 +28,26 @@ properties: maxItems: 1
interrupts:
minItems: 3 items:
- description: Job interrupt
- description: MMU interrupt
- description: GPU interrupt
- description: Event interruptinterrupt-names:
minItems: 3 items:
- const: job
- const: mmu
- const: gpu
- const: eventclocks:
- maxItems: 1
minItems: 1
maxItems: 3
clock-names: true
mali-supply: true
@@ -52,7 +60,10 @@ properties: maxItems: 3
resets:
- maxItems: 2
minItems: 1
maxItems: 3
reset-names: true
"#cooling-cells": const: 2
@@ -94,6 +105,36 @@ allOf: then: required: - resets
- if:
properties:compatible:contains:const: renesas,r9a07g044-mali- then:
properties:interrupts:minItems: 4interrupt-names:minItems: 4clocks:minItems: 3clock-names:items:- const: gpu- const: bus- const: bus_aceresets:minItems: 3reset-names:items:- const: rst- const: axi_rst- const: ace_rstrequired:- clock-names- power-domains- resets- reset-names
- if: properties: compatible:
-- 2.17.1
Hi Rob,
Subject: Re: [PATCH v3 1/3] dt-bindings: gpu: mali-bifrost: Document RZ/G2L support
On Fri, Dec 10, 2021 at 02:44:06PM +0000, Biju Das wrote:
Hi All,
Gentle ping.
2 days later is not a gentle ping. If you want to check status, go look at PW[1]. If it is in there, it's in my queue (only about 100 patches ATM).
Sorry. Next time will take care.
Cheers, Biju
[1] https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwor k.ozlabs.org%2Fproject%2Fdevicetree- bindings%2Flist%2F&data=04%7C01%7Cbiju.das.jz%40bp.renesas.com%7C4c2f7 b12ae0c4fd541d608d9bf36f549%7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C6 37751065028707898%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2lu MzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&sdata=1rccc5jxHMAu111IJrebdW PwTP%2BrQj8uG9iSuMO58EM%3D&reserved=0
Cheers, Biju
Subject: [PATCH v3 1/3] dt-bindings: gpu: mali-bifrost: Document RZ/G2L support
The Renesas RZ/G2{L, LC} SoC (a.k.a R9A07G044) has a Bifrost Mali-G31 GPU, add a compatible string for it.
Signed-off-by: Biju Das biju.das.jz@bp.renesas.com Reviewed-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com
v2->v3:
- Moved optional clock-names and reset-names to SoC-specific
conditional schemas.
- minimum number of reset for the generic GPU is set to 1.
- Documented number of clocks, resets, interrupts and
interrupt-names in RZ/G2L SoC-specific conditional schemas. v1->v2:
- Updated minItems for resets as 2
- Documented optional property reset-names
- Documented reset-names as required property for RZ/G2L SoC.
.../bindings/gpu/arm,mali-bifrost.yaml | 45
++++++++++++++++++-
1 file changed, 43 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml index 6f98dd55fb4c..63a08f3f321d 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml +++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml @@ -19,6 +19,7 @@ properties: - amlogic,meson-g12a-mali - mediatek,mt8183-mali - realtek,rtd1619-mali
- renesas,r9a07g044-mali - rockchip,px30-mali - rockchip,rk3568-mali - const: arm,mali-bifrost # Mali Bifrost GPU model/revisionis fully discoverable @@ -27,19 +28,26 @@ properties: maxItems: 1
interrupts:
minItems: 3 items:
- description: Job interrupt
- description: MMU interrupt
- description: GPU interrupt
- description: Event interruptinterrupt-names:
minItems: 3 items:
- const: job
- const: mmu
- const: gpu
- const: eventclocks:
- maxItems: 1
minItems: 1
maxItems: 3
clock-names: true
mali-supply: true
@@ -52,7 +60,10 @@ properties: maxItems: 3
resets:
- maxItems: 2
minItems: 1
maxItems: 3
reset-names: true
"#cooling-cells": const: 2
@@ -94,6 +105,36 @@ allOf: then: required: - resets
- if:
properties:compatible:contains:const: renesas,r9a07g044-mali- then:
properties:interrupts:minItems: 4interrupt-names:minItems: 4clocks:minItems: 3clock-names:items:- const: gpu- const: bus- const: bus_aceresets:minItems: 3reset-names:items:- const: rst- const: axi_rst- const: ace_rstrequired:- clock-names- power-domains- resets- reset-names
- if: properties: compatible:
-- 2.17.1
On 08/12/2021 10:40, Biju Das wrote:
The Renesas RZ/G2{L, LC} SoC (a.k.a R9A07G044) has a Bifrost Mali-G31 GPU, add a compatible string for it.
Signed-off-by: Biju Das biju.das.jz@bp.renesas.com Reviewed-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com
v2->v3:
- Moved optional clock-names and reset-names to SoC-specific conditional schemas.
- minimum number of reset for the generic GPU is set to 1.
- Documented number of clocks, resets, interrupts and interrupt-names in RZ/G2L SoC-specific conditional schemas.
v1->v2:
- Updated minItems for resets as 2
- Documented optional property reset-names
- Documented reset-names as required property for RZ/G2L SoC.
.../bindings/gpu/arm,mali-bifrost.yaml | 45 ++++++++++++++++++- 1 file changed, 43 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml index 6f98dd55fb4c..63a08f3f321d 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml +++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml @@ -19,6 +19,7 @@ properties: - amlogic,meson-g12a-mali - mediatek,mt8183-mali - realtek,rtd1619-mali
- renesas,r9a07g044-mali - rockchip,px30-mali - rockchip,rk3568-mali - const: arm,mali-bifrost # Mali Bifrost GPU model/revision is fully discoverable@@ -27,19 +28,26 @@ properties: maxItems: 1
interrupts:
minItems: 3 items:
- description: Job interrupt
- description: MMU interrupt
- description: GPU interrupt
- description: Event interruptinterrupt-names:
minItems: 3 items:
- const: job
- const: mmu
- const: gpu
- const: event
FWIW: I think it's fair to add the "event" interrupt even if it isn't included in the bindings for kbase. While pretty much useless on Bifrost it is a hardware feature and in theory it could be used.
Reviewed-by: Steven Price steven.price@arm.com
Steve
clocks:
- maxItems: 1
minItems: 1
maxItems: 3
clock-names: true
mali-supply: true
@@ -52,7 +60,10 @@ properties: maxItems: 3
resets:
- maxItems: 2
minItems: 1
maxItems: 3
reset-names: true
"#cooling-cells": const: 2
@@ -94,6 +105,36 @@ allOf: then: required: - resets
- if:
properties:compatible:contains:const: renesas,r9a07g044-mali- then:
properties:interrupts:minItems: 4interrupt-names:minItems: 4clocks:minItems: 3clock-names:items:- const: gpu- const: bus- const: bus_aceresets:minItems: 3reset-names:items:- const: rst- const: axi_rst- const: ace_rstrequired:- clock-names- power-domains- resets- reset-names
- if: properties: compatible:
On Wed, 08 Dec 2021 10:40:24 +0000, Biju Das wrote:
The Renesas RZ/G2{L, LC} SoC (a.k.a R9A07G044) has a Bifrost Mali-G31 GPU, add a compatible string for it.
Signed-off-by: Biju Das biju.das.jz@bp.renesas.com Reviewed-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com
v2->v3:
- Moved optional clock-names and reset-names to SoC-specific conditional schemas.
- minimum number of reset for the generic GPU is set to 1.
- Documented number of clocks, resets, interrupts and interrupt-names in RZ/G2L SoC-specific conditional schemas.
v1->v2:
- Updated minItems for resets as 2
- Documented optional property reset-names
- Documented reset-names as required property for RZ/G2L SoC.
.../bindings/gpu/arm,mali-bifrost.yaml | 45 ++++++++++++++++++- 1 file changed, 43 insertions(+), 2 deletions(-)
Applied, thanks!
On Thu, Dec 16, 2021 at 2:37 PM Geert Uytterhoeven geert@linux-m68k.org wrote:
From: Biju Das biju.das.jz@bp.renesas.com
RZ/G2L SoC embeds Mali-G31 bifrost GPU. This patch series aims to add support for the same
Oops, please ignore this email. Sorry for the noise.
Gr{oetje,eeting}s,
Geert
-- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
On Thu, Dec 16, 2021 at 2:41 PM Geert Uytterhoeven geert@linux-m68k.org wrote:
From: Biju Das biju.das.jz@bp.renesas.com
RZ/G2L SoC embeds Mali-G31 bifrost GPU. This patch series aims to add support for the same
Oops, please ignore this email. Sorry for the noise.
Gr{oetje,eeting}s,
Geert
-- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
On Thu, Dec 16, 2021 at 2:44 PM Geert Uytterhoeven geert@linux-m68k.org wrote:
From: Biju Das biju.das.jz@bp.renesas.com
RZ/G2L SoC embeds Mali-G31 bifrost GPU. This patch series aims to add support for the same
Oops, please ignore this email. Sorry for the noise.
Gr{oetje,eeting}s,
Geert
-- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Hi Biju,
On Wed, 8 Dec 2021 at 10:40, Biju Das biju.das.jz@bp.renesas.com wrote:
RZ/G2L SoC embeds Mali-G31 bifrost GPU. This patch series aims to add support for the same
It is tested with latest drm-misc-next + mesa 21.3.0 + out of tree patch for (du + DSI) + platform specific mesa configuration for RZ/G2L.
Could you please post the 'platform-specific Mesa configuration' patches as a merge request to Mesa? Thanks.
Cheers, Daniel
Hi Daniel Stone,
Thanks for the feedback.
Subject: Re: [PATCH v3 0/3] Add Mali-G31 GPU support for RZ/G2L SoC
Hi Biju,
On Wed, 8 Dec 2021 at 10:40, Biju Das biju.das.jz@bp.renesas.com wrote:
RZ/G2L SoC embeds Mali-G31 bifrost GPU. This patch series aims to add support for the same
It is tested with latest drm-misc-next + mesa 21.3.0 + out of tree patch for (du + DSI) + platform specific mesa configuration for RZ/G2L.
Could you please post the 'platform-specific Mesa configuration' patches as a merge request to Mesa?
Sure will send a merge request to Mesa.
Regards, Biju
dri-devel@lists.freedesktop.org
-
Biju Das -
Daniel Stone -
Geert Uytterhoeven -
Rob Herring -
Steven Price