The bridge chip ANX7625 require the line packets ending at the sametime or ANX7625 will shift the screen.
Change-Id: Ia324ad28fbff54140feedb9a1d6bfb2b246d0447 Signed-off-by: Jitao Shi jitao.shi@mediatek.com --- drivers/gpu/drm/mediatek/mtk_dsi.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c index a1ff152ef468..e825a80862de 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -194,6 +194,8 @@ struct mtk_dsi { struct clk *hs_clk;
u32 data_rate; + /* force dsi line end without dsi_null data */ + bool force_dsi_end_without_null;
unsigned long mode_flags; enum mipi_dsi_pixel_format format; @@ -495,6 +497,13 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi) DRM_WARN("HFP + HBP less than d-phy, FPS will under 60Hz\n"); }
+ if (dsi->force_dsi_end_without_null) { + horizontal_sync_active_byte = roundup(horizontal_sync_active_byte, dsi->lanes) - 2; + horizontal_frontporch_byte = roundup(horizontal_frontporch_byte, dsi->lanes) - 2; + horizontal_backporch_byte = roundup(horizontal_backporch_byte, dsi->lanes) - 2; + horizontal_backporch_byte -= (vm->hactive * dsi_tmp_buf_bpp + 2) % dsi->lanes; + } + writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC); writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC); writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC); @@ -1091,6 +1100,9 @@ static int mtk_dsi_probe(struct platform_device *pdev) dsi->bridge.of_node = dev->of_node; dsi->bridge.type = DRM_MODE_CONNECTOR_DSI;
+ dsi->force_dsi_end_without_null = of_property_read_bool(dev->of_node, + "force_dsi_end_without_null"); + drm_bridge_add(&dsi->bridge);
ret = component_add(&pdev->dev, &mtk_dsi_component_ops);
Hi, Jitao:
Jitao Shi jitao.shi@mediatek.com 於 2021年4月7日 週三 下午10:37寫道:
The bridge chip ANX7625 require the line packets ending at the sametime or ANX7625 will shift the screen.
Change-Id: Ia324ad28fbff54140feedb9a1d6bfb2b246d0447 Signed-off-by: Jitao Shi jitao.shi@mediatek.com
drivers/gpu/drm/mediatek/mtk_dsi.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c index a1ff152ef468..e825a80862de 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -194,6 +194,8 @@ struct mtk_dsi { struct clk *hs_clk;
u32 data_rate;
/* force dsi line end without dsi_null data */
bool force_dsi_end_without_null; unsigned long mode_flags; enum mipi_dsi_pixel_format format;
@@ -495,6 +497,13 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi) DRM_WARN("HFP + HBP less than d-phy, FPS will under 60Hz\n"); }
if (dsi->force_dsi_end_without_null) {
horizontal_sync_active_byte = roundup(horizontal_sync_active_byte, dsi->lanes) - 2;
horizontal_frontporch_byte = roundup(horizontal_frontporch_byte, dsi->lanes) - 2;
horizontal_backporch_byte = roundup(horizontal_backporch_byte, dsi->lanes) - 2;
horizontal_backporch_byte -= (vm->hactive * dsi_tmp_buf_bpp + 2) % dsi->lanes;
}
writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC); writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC); writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC);
@@ -1091,6 +1100,9 @@ static int mtk_dsi_probe(struct platform_device *pdev) dsi->bridge.of_node = dev->of_node; dsi->bridge.type = DRM_MODE_CONNECTOR_DSI;
dsi->force_dsi_end_without_null = of_property_read_bool(dev->of_node,
"force_dsi_end_without_null");
If force_dsi_end_without_null is caused by ANX7625, I think we should get this information from ANX7625.
Regards, Chun-Kuang.
drm_bridge_add(&dsi->bridge); ret = component_add(&pdev->dev, &mtk_dsi_component_ops);
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