[Mesa-dev] [PATCH 1/7] i965/vs: Do round-robin register allocation on gen6+ like we do in the FS.

[Kenneth Graunke]

On 04/30/2013 09:15 AM, Eric Anholt wrote:
> This will free instruction scheduling to make better choices.  No
> statistically significant performance difference on GLB2.7 (n=93).
> ---
>   src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp |    4 ++++
>   1 file changed, 4 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
> index ac3d401..7149d46 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
> @@ -102,6 +102,8 @@ brw_alloc_reg_set_for_classes(struct brw_context *brw,
>   			      int class_count,
>   			      int base_reg_count)
>   {
> +   struct intel_context *intel = &brw->intel;
> +
>      /* Compute the total number of registers across all classes. */
>      int ra_reg_count = 0;
>      for (int i = 0; i < class_count; i++) {
> @@ -112,6 +114,8 @@ brw_alloc_reg_set_for_classes(struct brw_context *brw,
>      brw->vs.ra_reg_to_grf = ralloc_array(brw, uint8_t, ra_reg_count);
>      ralloc_free(brw->vs.regs);
>      brw->vs.regs = ra_alloc_reg_set(brw, ra_reg_count);
> +   if (intel->gen >= 6)
> +      ra_set_allocate_round_robin(brw->vs.regs);
>      ralloc_free(brw->vs.classes);
>      brw->vs.classes = ralloc_array(brw, int, class_count + 1);

Thanks for doing this!

For the series:
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>