[Mesa-dev] [PATCH] i965: Enable fast clears on non-8x4-aligned sizes.

[Chad Versace]

On 05/02/2013 04:58 PM, Kenneth Graunke wrote:
> On 05/02/2013 01:58 PM, Eric Anholt wrote:
>> Improves glb2.7 performance at a misaligned size by 2.3% +/- 0.7% (n=11).
>> The workaround was to avoid bad primitive/surface sizes, but that's worked
>> around as of a14dc4f92cdad6177d83f051a088a66e31a973bc.  (One might note
>> that pre-gen7 we don't know that the right half of an 8x4 at the right
>> edge is actually our pixels, but we're already clobbering those pixels for
>> depth resolves anyway and more work would be required to avoid that).
>> ---
>>   src/mesa/drivers/dri/i965/brw_clear.c | 13 -------------
>>   1 file changed, 13 deletions(-)
>>
>> diff --git a/src/mesa/drivers/dri/i965/brw_clear.c b/src/mesa/drivers/dri/i965/brw_clear.c
>> index 4ee456a..2b999bf 100644
>> --- a/src/mesa/drivers/dri/i965/brw_clear.c
>> +++ b/src/mesa/drivers/dri/i965/brw_clear.c
>> @@ -128,19 +128,6 @@ brw_fast_clear_depth(struct gl_context *ctx)
>>         return false;
>>      }
>>
>> -   /* The rendered area has to be 8x4 samples, not resolved pixels, so we look
>> -    * at the miptree slice dimensions instead of renderbuffer size.
>> -    */
>> -   if (mt->level[depth_irb->mt_level].width % 8 != 0 ||
>> -       mt->level[depth_irb->mt_level].height % 4 != 0) {
>> -      perf_debug("Failed to fast clear depth due to width/height %d,%d not "
>> -                 "being aligned to 8,4.  Possible 5%% performance win if "
>> -                 "avoided\n",
>> -                 mt->level[depth_irb->mt_level].width,
>> -                 mt->level[depth_irb->mt_level].height);
>> -      return false;
>> -   }
>> -
>>      uint32_t depth_clear_value;
>>      switch (mt->format) {
>>      case MESA_FORMAT_Z32_FLOAT_X24S8:
>>
>
> Would be worth regression testing on Gen6.
>
> Really glad to see this working.
> Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

Reviewed-by: Chad Versace <chad.versace at linux.intel.com>