[Mesa-dev] [PATCH] i965: Fix hangs on HSW since the gen6 blorp fix.

[Eric Anholt]

The constant packets for gen6 are too small for gen7, and while IVB seems
happy with them HSW blows up.  Just restore the HSW path to what it was
before the gen6 change, by making gen7-specific functions to set up these
stages.
---

The alternative here would be to emit the correct lengths of packets
in these new functions.  But we're not emitting constants for other
disabled stages on gen7+, so I'm leaning toward this variant.

 src/mesa/drivers/dri/i965/gen7_blorp.cpp | 57 ++++++++++++++++++++++++++++++--
 1 file changed, 55 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index 1c23866..330e3d5 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -276,6 +276,39 @@ gen7_blorp_emit_sampler_state(struct brw_context *brw,
 }
 
 
+/* 3DSTATE_VS
+ *
+ * Disable vertex shader.
+ */
+static void
+gen7_blorp_emit_vs_disable(struct brw_context *brw,
+                           const brw_blorp_params *params)
+{
+   struct intel_context *intel = &brw->intel;
+
+   if (intel->gen == 6) {
+      /* From the BSpec, Volume 2a, Part 3 "Vertex Shader", Section
+       * 3DSTATE_VS, Dword 5.0 "VS Function Enable":
+       *
+       *   [DevSNB] A pipeline flush must be programmed prior to a
+       *   3DSTATE_VS command that causes the VS Function Enable to
+       *   toggle. Pipeline flush can be executed by sending a PIPE_CONTROL
+       *   command with CS stall bit set and a post sync operation.
+       */
+      intel_emit_post_sync_nonzero_flush(intel);
+   }
+
+   BEGIN_BATCH(6);
+   OUT_BATCH(_3DSTATE_VS << 16 | (6 - 2));
+   OUT_BATCH(0);
+   OUT_BATCH(0);
+   OUT_BATCH(0);
+   OUT_BATCH(0);
+   OUT_BATCH(0);
+   ADVANCE_BATCH();
+}
+
+
 /* 3DSTATE_HS
  *
  * Disable the hull shader.
@@ -337,6 +370,26 @@ gen7_blorp_emit_ds_disable(struct brw_context *brw,
    ADVANCE_BATCH();
 }
 
+/* 3DSTATE_GS
+ *
+ * Disable the geometry shader.
+ */
+static void
+gen7_blorp_emit_gs_disable(struct brw_context *brw,
+                           const brw_blorp_params *params)
+{
+   struct intel_context *intel = &brw->intel;
+
+   BEGIN_BATCH(7);
+   OUT_BATCH(_3DSTATE_GS << 16 | (7 - 2));
+   OUT_BATCH(0);
+   OUT_BATCH(0);
+   OUT_BATCH(0);
+   OUT_BATCH(0);
+   OUT_BATCH(0);
+   OUT_BATCH(0);
+   ADVANCE_BATCH();
+}
 
 /* 3DSTATE_STREAMOUT
  *
@@ -784,11 +837,11 @@ gen7_blorp_exec(struct intel_context *intel,
                                        wm_surf_offset_texture);
       sampler_offset = gen7_blorp_emit_sampler_state(brw, params);
    }
-   gen6_blorp_emit_vs_disable(brw, params);
+   gen7_blorp_emit_vs_disable(brw, params);
    gen7_blorp_emit_hs_disable(brw, params);
    gen7_blorp_emit_te_disable(brw, params);
    gen7_blorp_emit_ds_disable(brw, params);
-   gen6_blorp_emit_gs_disable(brw, params);
+   gen7_blorp_emit_gs_disable(brw, params);
    gen7_blorp_emit_streamout_disable(brw, params);
    gen6_blorp_emit_clip_disable(brw, params);
    gen7_blorp_emit_sf_config(brw, params);
-- 
1.8.3.rc0