[Mesa-dev] [PATCH] R600/SI: Add lit test coverage for the remaining patterns added recently

[Michel Dänzer]

From: Michel Dänzer <michel.daenzer at amd.com>

Signed-off-by: Michel Dänzer <michel.daenzer at amd.com>
---
 test/CodeGen/R600/llvm.AMDGPU.imax.ll  | 21 +++++++++++++++++++++
 test/CodeGen/R600/llvm.AMDGPU.imin.ll  | 21 +++++++++++++++++++++
 test/CodeGen/R600/llvm.AMDGPU.trunc.ll | 22 +++++++++++-----------
 test/CodeGen/R600/llvm.AMDGPU.umax.ll  | 21 +++++++++++++++++++++
 test/CodeGen/R600/llvm.AMDGPU.umin.ll  | 21 +++++++++++++++++++++
 test/CodeGen/R600/uitofp.ll            | 16 ++++++++++++++++
 6 files changed, 111 insertions(+), 11 deletions(-)
 create mode 100644 test/CodeGen/R600/llvm.AMDGPU.imax.ll
 create mode 100644 test/CodeGen/R600/llvm.AMDGPU.imin.ll
 create mode 100644 test/CodeGen/R600/llvm.AMDGPU.umax.ll
 create mode 100644 test/CodeGen/R600/llvm.AMDGPU.umin.ll
 create mode 100644 test/CodeGen/R600/uitofp.ll

diff --git a/test/CodeGen/R600/llvm.AMDGPU.imax.ll b/test/CodeGen/R600/llvm.AMDGPU.imax.ll
new file mode 100644
index 0000000..3e854c8
--- /dev/null
+++ b/test/CodeGen/R600/llvm.AMDGPU.imax.ll
@@ -0,0 +1,21 @@
+;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
+
+;CHECK: V_MAX_I32_e32
+
+define void @main(i32 %p0, i32 %p1) #0 {
+main_body:
+  %0 = call i32 @llvm.AMDGPU.imax(i32 %p0, i32 %p1)
+  %1 = bitcast i32 %0 to float
+  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %1, float %1, float %1, float %1)
+  ret void
+}
+
+; Function Attrs: readnone
+declare i32 @llvm.AMDGPU.imax(i32, i32) #1
+
+declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
+
+attributes #0 = { "ShaderType"="0" }
+attributes #1 = { readnone }
+
+!0 = metadata !{metadata !"const", null, i32 1}
diff --git a/test/CodeGen/R600/llvm.AMDGPU.imin.ll b/test/CodeGen/R600/llvm.AMDGPU.imin.ll
new file mode 100644
index 0000000..e227bf8
--- /dev/null
+++ b/test/CodeGen/R600/llvm.AMDGPU.imin.ll
@@ -0,0 +1,21 @@
+;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
+
+;CHECK: V_MIN_I32_e32
+
+define void @main(i32 %p0, i32 %p1) #0 {
+main_body:
+  %0 = call i32 @llvm.AMDGPU.imin(i32 %p0, i32 %p1)
+  %1 = bitcast i32 %0 to float
+  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %1, float %1, float %1, float %1)
+  ret void
+}
+
+; Function Attrs: readnone
+declare i32 @llvm.AMDGPU.imin(i32, i32) #1
+
+declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
+
+attributes #0 = { "ShaderType"="0" }
+attributes #1 = { readnone }
+
+!0 = metadata !{metadata !"const", null, i32 1}
diff --git a/test/CodeGen/R600/llvm.AMDGPU.trunc.ll b/test/CodeGen/R600/llvm.AMDGPU.trunc.ll
index ff22a69..cdc03f8 100644
--- a/test/CodeGen/R600/llvm.AMDGPU.trunc.ll
+++ b/test/CodeGen/R600/llvm.AMDGPU.trunc.ll
@@ -1,16 +1,16 @@
-;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
+; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=R600-CHECK %s
+; RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s
 
-;CHECK: TRUNC * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+; R600-CHECK: @amdgpu_trunc
+; R600-CHECK: TRUNC * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+; SI-CHECK: @amdgpu_trunc
+; SI-CHECK: V_TRUNC_F32
 
-define void @test() {
-   %r0 = call float @llvm.R600.load.input(i32 0)
-   %r1 = call float @llvm.AMDGPU.trunc( float %r0)
-   call void @llvm.AMDGPU.store.output(float %r1, i32 0)
-   ret void
+define void @amdgpu_trunc(float addrspace(1)* %out, float %x) {
+entry:
+  %0 = call float @llvm.AMDGPU.trunc(float %x)
+  store float %0, float addrspace(1)* %out
+  ret void
 }
 
-declare float @llvm.R600.load.input(i32) readnone
-
-declare void @llvm.AMDGPU.store.output(float, i32)
-
 declare float @llvm.AMDGPU.trunc(float ) readnone
diff --git a/test/CodeGen/R600/llvm.AMDGPU.umax.ll b/test/CodeGen/R600/llvm.AMDGPU.umax.ll
new file mode 100644
index 0000000..7699c04
--- /dev/null
+++ b/test/CodeGen/R600/llvm.AMDGPU.umax.ll
@@ -0,0 +1,21 @@
+;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
+
+;CHECK: V_MAX_U32_e32
+
+define void @main(i32 %p0, i32 %p1) #0 {
+main_body:
+  %0 = call i32 @llvm.AMDGPU.umax(i32 %p0, i32 %p1)
+  %1 = bitcast i32 %0 to float
+  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %1, float %1, float %1, float %1)
+  ret void
+}
+
+; Function Attrs: readnone
+declare i32 @llvm.AMDGPU.umax(i32, i32) #1
+
+declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
+
+attributes #0 = { "ShaderType"="0" }
+attributes #1 = { readnone }
+
+!0 = metadata !{metadata !"const", null, i32 1}
diff --git a/test/CodeGen/R600/llvm.AMDGPU.umin.ll b/test/CodeGen/R600/llvm.AMDGPU.umin.ll
new file mode 100644
index 0000000..a911ad9
--- /dev/null
+++ b/test/CodeGen/R600/llvm.AMDGPU.umin.ll
@@ -0,0 +1,21 @@
+;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
+
+;CHECK: V_MIN_U32_e32
+
+define void @main(i32 %p0, i32 %p1) #0 {
+main_body:
+  %0 = call i32 @llvm.AMDGPU.umin(i32 %p0, i32 %p1)
+  %1 = bitcast i32 %0 to float
+  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %1, float %1, float %1, float %1)
+  ret void
+}
+
+; Function Attrs: readnone
+declare i32 @llvm.AMDGPU.umin(i32, i32) #1
+
+declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
+
+attributes #0 = { "ShaderType"="0" }
+attributes #1 = { readnone }
+
+!0 = metadata !{metadata !"const", null, i32 1}
diff --git a/test/CodeGen/R600/uitofp.ll b/test/CodeGen/R600/uitofp.ll
new file mode 100644
index 0000000..6cf9e6a
--- /dev/null
+++ b/test/CodeGen/R600/uitofp.ll
@@ -0,0 +1,16 @@
+;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
+
+;CHECK: V_CVT_F32_U32_e32
+
+define void @main(i32 %p) #0 {
+main_body:
+  %0 = uitofp i32 %p to float
+  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %0, float %0, float %0, float %0)
+  ret void
+}
+
+declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
+
+attributes #0 = { "ShaderType"="0" }
+
+!0 = metadata !{metadata !"const", null, i32 1}
-- 
1.8.3.rc1