[Mesa-dev] R600: Various improvements
Tom Stellard
tom at stellard.net
Tue May 14 07:34:15 PDT 2013
> From 8aa41148651150eb19332436c76fe490d4b54b1e Mon Sep 17 00:00:00 2001
> From: Vincent Lejeune <vljn at ovi.com>
> Date: Sun, 12 May 2013 16:29:50 +0200
> Subject: [PATCH 1/2] R600: Rename 128 bit registers.
>
> Almost all instructions that takes a 128 bits reg as input (fetch, export...)
> have the abilities to swizzle their argument and output. Instead of printing
> default swizzle for each 128 bits reg, rename T*.XYZW to T* and let instructions
> print potentially optimized swizzle themselve.
Typo here: swizzle themselve -> swizzles themselves
Both patches are:
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
> ---
> lib/Target/R600/R600Instructions.td | 17 ++++++++---------
> lib/Target/R600/R600RegisterInfo.td | 2 +-
> test/CodeGen/R600/llvm.AMDGPU.tex.ll | 32 ++++++++++++++++----------------
> 3 files changed, 25 insertions(+), 26 deletions(-)
>
> diff --git a/lib/Target/R600/R600Instructions.td b/lib/Target/R600/R600Instructions.td
> index 86e4b4a..abaa94b 100644
> --- a/lib/Target/R600/R600Instructions.td
> +++ b/lib/Target/R600/R600Instructions.td
> @@ -1750,8 +1750,7 @@ let usesCustomInserter = 1 in {
>
> class RAT_WRITE_CACHELESS_eg <dag ins, bits<4> comp_mask, string name,
> list<dag> pattern>
> - : EG_CF_RAT <0x57, 0x2, 0, (outs), ins,
> - !strconcat(name, " $rw_gpr, $index_gpr, $eop"), pattern> {
> + : EG_CF_RAT <0x57, 0x2, 0, (outs), ins, name, pattern> {
> let RIM = 0;
> // XXX: Have a separate instruction for non-indexed writes.
> let TYPE = 1;
> @@ -1771,19 +1770,19 @@ class RAT_WRITE_CACHELESS_eg <dag ins, bits<4> comp_mask, string name,
> // 32-bit store
> def RAT_WRITE_CACHELESS_32_eg : RAT_WRITE_CACHELESS_eg <
> (ins R600_TReg32_X:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop),
> - 0x1, "RAT_WRITE_CACHELESS_32_eg",
> + 0x1, "RAT_WRITE_CACHELESS_32_eg $rw_gpr, $index_gpr, $eop",
> [(global_store i32:$rw_gpr, i32:$index_gpr)]
> >;
>
> //128-bit store
> def RAT_WRITE_CACHELESS_128_eg : RAT_WRITE_CACHELESS_eg <
> (ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop),
> - 0xf, "RAT_WRITE_CACHELESS_128",
> + 0xf, "RAT_WRITE_CACHELESS_128 $rw_gpr.XYZW, $index_gpr, $eop",
> [(global_store v4i32:$rw_gpr, i32:$index_gpr)]
> >;
>
> class VTX_READ_eg <string name, bits<8> buffer_id, dag outs, list<dag> pattern>
> - : InstR600ISA <outs, (ins MEMxi:$ptr), name#" $dst, $ptr", pattern>,
> + : InstR600ISA <outs, (ins MEMxi:$ptr), name, pattern>,
> VTX_WORD1_GPR, VTX_WORD0 {
>
> // Static fields
> @@ -1838,7 +1837,7 @@ class VTX_READ_eg <string name, bits<8> buffer_id, dag outs, list<dag> pattern>
> }
>
> class VTX_READ_8_eg <bits<8> buffer_id, list<dag> pattern>
> - : VTX_READ_eg <"VTX_READ_8", buffer_id, (outs R600_TReg32_X:$dst),
> + : VTX_READ_eg <"VTX_READ_8 $dst, $ptr", buffer_id, (outs R600_TReg32_X:$dst),
> pattern> {
>
> let MEGA_FETCH_COUNT = 1;
> @@ -1850,7 +1849,7 @@ class VTX_READ_8_eg <bits<8> buffer_id, list<dag> pattern>
> }
>
> class VTX_READ_16_eg <bits<8> buffer_id, list<dag> pattern>
> - : VTX_READ_eg <"VTX_READ_16", buffer_id, (outs R600_TReg32_X:$dst),
> + : VTX_READ_eg <"VTX_READ_16 $dst, $ptr", buffer_id, (outs R600_TReg32_X:$dst),
> pattern> {
> let MEGA_FETCH_COUNT = 2;
> let DST_SEL_X = 0;
> @@ -1862,7 +1861,7 @@ class VTX_READ_16_eg <bits<8> buffer_id, list<dag> pattern>
> }
>
> class VTX_READ_32_eg <bits<8> buffer_id, list<dag> pattern>
> - : VTX_READ_eg <"VTX_READ_32", buffer_id, (outs R600_TReg32_X:$dst),
> + : VTX_READ_eg <"VTX_READ_32 $dst, $ptr", buffer_id, (outs R600_TReg32_X:$dst),
> pattern> {
>
> let MEGA_FETCH_COUNT = 4;
> @@ -1883,7 +1882,7 @@ class VTX_READ_32_eg <bits<8> buffer_id, list<dag> pattern>
> }
>
> class VTX_READ_128_eg <bits<8> buffer_id, list<dag> pattern>
> - : VTX_READ_eg <"VTX_READ_128", buffer_id, (outs R600_Reg128:$dst),
> + : VTX_READ_eg <"VTX_READ_128 $dst.XYZW, $ptr", buffer_id, (outs R600_Reg128:$dst),
> pattern> {
>
> let MEGA_FETCH_COUNT = 16;
> diff --git a/lib/Target/R600/R600RegisterInfo.td b/lib/Target/R600/R600RegisterInfo.td
> index bfc546b..df6004b 100644
> --- a/lib/Target/R600/R600RegisterInfo.td
> +++ b/lib/Target/R600/R600RegisterInfo.td
> @@ -35,7 +35,7 @@ foreach Index = 0-127 in {
> Chan>;
> }
> // 128-bit Temporary Registers
> - def T#Index#_XYZW : R600Reg_128 <"T"#Index#".XYZW",
> + def T#Index#_XYZW : R600Reg_128 <"T"#Index#"",
> [!cast<Register>("T"#Index#"_X"),
> !cast<Register>("T"#Index#"_Y"),
> !cast<Register>("T"#Index#"_Z"),
> diff --git a/test/CodeGen/R600/llvm.AMDGPU.tex.ll b/test/CodeGen/R600/llvm.AMDGPU.tex.ll
> index 74331fa..81fd43d 100644
> --- a/test/CodeGen/R600/llvm.AMDGPU.tex.ll
> +++ b/test/CodeGen/R600/llvm.AMDGPU.tex.ll
> @@ -1,21 +1,21 @@
> ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
>
> -;CHECK: TEX_SAMPLET{{[0-9]+\.XYZW, T[0-9]+\.XYZW}}, 0, 0, 1
> -;CHECK: TEX_SAMPLET{{[0-9]+\.XYZW, T[0-9]+\.XYZW}}, 0, 0, 2
> -;CHECK: TEX_SAMPLET{{[0-9]+\.XYZW, T[0-9]+\.XYZW}}, 0, 0, 3
> -;CHECK: TEX_SAMPLET{{[0-9]+\.XYZW, T[0-9]+\.XYZW}}, 0, 0, 4
> -;CHECK: TEX_SAMPLET{{[0-9]+\.XYZW, T[0-9]+\.XYZW}}, 0, 0, 5
> -;CHECK: TEX_SAMPLE_CT{{[0-9]+\.XYZW, T[0-9]+\.XYZW}}, 0, 0, 6
> -;CHECK: TEX_SAMPLE_CT{{[0-9]+\.XYZW, T[0-9]+\.XYZW}}, 0, 0, 7
> -;CHECK: TEX_SAMPLE_CT{{[0-9]+\.XYZW, T[0-9]+\.XYZW}}, 0, 0, 8
> -;CHECK: TEX_SAMPLET{{[0-9]+\.XYZW, T[0-9]+\.XYZW}}, 0, 0, 9
> -;CHECK: TEX_SAMPLET{{[0-9]+\.XYZW, T[0-9]+\.XYZW}}, 0, 0, 10
> -;CHECK: TEX_SAMPLE_CT{{[0-9]+\.XYZW, T[0-9]+\.XYZW}}, 0, 0, 11
> -;CHECK: TEX_SAMPLE_CT{{[0-9]+\.XYZW, T[0-9]+\.XYZW}}, 0, 0, 12
> -;CHECK: TEX_SAMPLE_CT{{[0-9]+\.XYZW, T[0-9]+\.XYZW}}, 0, 0, 13
> -;CHECK: TEX_SAMPLET{{[0-9]+\.XYZW, T[0-9]+\.XYZW}}, 0, 0, 14
> -;CHECK: TEX_SAMPLET{{[0-9]+\.XYZW, T[0-9]+\.XYZW}}, 0, 0, 15
> -;CHECK: TEX_SAMPLET{{[0-9]+\.XYZW, T[0-9]+\.XYZW}}, 0, 0, 16
> +;CHECK: TEX_SAMPLET{{[0-9]+, T[0-9]+}}, 0, 0, 1
> +;CHECK: TEX_SAMPLET{{[0-9]+, T[0-9]+}}, 0, 0, 2
> +;CHECK: TEX_SAMPLET{{[0-9]+, T[0-9]+}}, 0, 0, 3
> +;CHECK: TEX_SAMPLET{{[0-9]+, T[0-9]+}}, 0, 0, 4
> +;CHECK: TEX_SAMPLET{{[0-9]+, T[0-9]+}}, 0, 0, 5
> +;CHECK: TEX_SAMPLE_CT{{[0-9]+, T[0-9]+}}, 0, 0, 6
> +;CHECK: TEX_SAMPLE_CT{{[0-9]+, T[0-9]+}}, 0, 0, 7
> +;CHECK: TEX_SAMPLE_CT{{[0-9]+, T[0-9]+}}, 0, 0, 8
> +;CHECK: TEX_SAMPLET{{[0-9]+, T[0-9]+}}, 0, 0, 9
> +;CHECK: TEX_SAMPLET{{[0-9]+, T[0-9]+}}, 0, 0, 10
> +;CHECK: TEX_SAMPLE_CT{{[0-9]+, T[0-9]+}}, 0, 0, 11
> +;CHECK: TEX_SAMPLE_CT{{[0-9]+, T[0-9]+}}, 0, 0, 12
> +;CHECK: TEX_SAMPLE_CT{{[0-9]+, T[0-9]+}}, 0, 0, 13
> +;CHECK: TEX_SAMPLET{{[0-9]+, T[0-9]+}}, 0, 0, 14
> +;CHECK: TEX_SAMPLET{{[0-9]+, T[0-9]+}}, 0, 0, 15
> +;CHECK: TEX_SAMPLET{{[0-9]+, T[0-9]+}}, 0, 0, 16
>
> define void @test(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
> %addr = load <4 x float> addrspace(1)* %in
> --
> 1.8.2.1
>
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