[Mesa-dev] [PATCH 2/2] i965/hsw: Set MOCS for surfaces

[Matt Turner]

On Thu, May 9, 2013 at 4:48 PM, Chad Versace
<chad.versace at linux.intel.com> wrote:
> The drivers was setting MOCS (Memory Object Control State) to 0 for all
> objects. This patch sets it as following:
>     renderbuffer, depthbuffer => LLC uncacheable, L3 cacheable
>     texture, stencil, hiz => LLC cacheable, L3 cacheable
>
> The goal here is to avoid blowing out the LLC with too-large buffers.
>
> Performance gains:
>     Haswell Harris Beach GT3
>     Android 4.2.2
>     kernel based on 3.8-4fc7c97
>
>     GLBenchmark 2.5.1 Egypt HD C24Z16 Offscreen DXT1
>         +32.0309% +/- 0.775397%,  n = 5, 95% confidence
>
>     GLBenchmark 2.7 T-Rex HD C24Z16 Offscreen Fixed timestep ETC1
>         +20.2435% +/- 0.821163%,  n = 5, 95% confidence
>
> Tested-by: Matt Turner <mattst88 at gmail.com>
> Signed-off-by: Chad Versace <chad.versace at linux.intel.com>
> ---
>
> This branch lives on my 'mocs' branch.
>
>
>  src/mesa/drivers/dri/i965/brw_context.c           | 31 +++++++++++++++++++++++
>  src/mesa/drivers/dri/i965/brw_context.h           | 13 ++++++++++
>  src/mesa/drivers/dri/i965/gen7_blorp.cpp          | 14 +++++++---
>  src/mesa/drivers/dri/i965/gen7_misc_state.c       | 16 ++++++++++--
>  src/mesa/drivers/dri/i965/gen7_wm_surface_state.c |  7 +++--
>  5 files changed, 74 insertions(+), 7 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
> index 4650553..edcf59d 100644
> --- a/src/mesa/drivers/dri/i965/brw_context.c
> +++ b/src/mesa/drivers/dri/i965/brw_context.c
> @@ -418,3 +418,34 @@ brwCreateContext(int api,
>     return true;
>  }
>
> +/**
> + * Get the region's Memory Object Control State.
> + */
> +uint32_t
> +brw_get_mocs(struct brw_context *brw,
> +             struct intel_region *region,
> +             enum brw_mocs_usage usage)
> +{
> +   struct intel_context *intel = &brw->intel;
> +   uint32_t mocs = 0;
> +
> +   if (intel->is_haswell) {
> +      /* This heuristic is dumb: it considers the buffer's usage, but not its
> +       * size. A more intelligent heuristic may give us better performance.
> +       */
> +      switch (usage) {
> +      case BRW_MOCS_USAGE_RB_SURFACE:
> +      case BRW_MOCS_USAGE_DEPTH:
> +         /* These surfaces are usually so large they blow out the LLC. */
> +         mocs = HSW_MOCS_LCC_UNCACHEABLE | HSW_MOCS_L3_CACHEABLE;
> +         break;
> +      case BRW_MOCS_USAGE_TEX_SURFACE:
> +      case BRW_MOCS_USAGE_HIZ:
> +      case BRW_MOCS_USAGE_STENCIL:
> +         mocs = HSW_MOCS_LCC_WB_TO_ALL | HSW_MOCS_L3_CACHEABLE;

A little late, but since these patches have my Tested-by I should
mention that I tested the previous versions only. These two patches
don't actually compile, since HSW_MOCS_LCC_WB_TO_ALL was renamed to
HSW_MOCS_LCC_WB_TO_LLC_ELLC but not updated here.