[Mesa-dev] [PATCH 1/2] r600g: add ISA info for RAT instructions
Vadim Girlin
vadimgirlin at gmail.com
Wed May 29 22:07:35 PDT 2013
On 05/30/2013 05:48 AM, Tom Stellard wrote:
> On Mon, May 27, 2013 at 02:15:21AM +0400, Vadim Girlin wrote:
>> This will help to improve dumps of the compute shaders,
>> also it will be required for complete handling of RAT instructions in sb.
>>
>> Signed-off-by: Vadim Girlin <vadimgirlin at gmail.com>
>> ---
>> src/gallium/drivers/r600/r600_isa.c | 19 ++++++
>> src/gallium/drivers/r600/r600_isa.h | 132 ++++++++++++++++++++++++++++++++++++
>> 2 files changed, 151 insertions(+)
>>
>> diff --git a/src/gallium/drivers/r600/r600_isa.c b/src/gallium/drivers/r600/r600_isa.c
>> index 4c6ccac..c99352f 100644
>> --- a/src/gallium/drivers/r600/r600_isa.c
>> +++ b/src/gallium/drivers/r600/r600_isa.c
>> @@ -81,6 +81,23 @@ int r600_isa_init(struct r600_context *ctx, struct r600_isa *isa) {
>> isa->cf_map[opc] = i + 1;
>> }
>>
>> + /* RAT instructions are not available on pre-evergreen */
>> + if (ctx->chip_class >= EVERGREEN) {
>> + unsigned column = isa->hw_class - ISA_CC_EVERGREEN;
>> +
>> + isa->rat_map = calloc(64, sizeof(unsigned));
>> + if (!isa->rat_map)
>> + return -1;
>> +
>> + for (i = 0; i < TABLE_SIZE(rat_op_table); ++i) {
>> + const struct rat_op_info *op = &rat_op_table[i];
>> + unsigned opc = op->opcode[column];
>> + if (opc == -1)
>> + continue;
>> + isa->rat_map[opc] = i + 1;
>> + }
>> + }
>> +
>> return 0;
>> }
>>
>> @@ -97,6 +114,8 @@ int r600_isa_destroy(struct r600_isa *isa) {
>> free(isa->fetch_map);
>> if (isa->cf_map)
>> free(isa->cf_map);
>> + if (isa->rat_map)
>> + free(isa->rat_map);
>>
>> free(isa);
>> return 0;
>> diff --git a/src/gallium/drivers/r600/r600_isa.h b/src/gallium/drivers/r600/r600_isa.h
>> index 8cccc9d..4055a04 100644
>> --- a/src/gallium/drivers/r600/r600_isa.h
>> +++ b/src/gallium/drivers/r600/r600_isa.h
>> @@ -147,6 +147,12 @@ enum cf_op_flags
>> CF_LOOP_START = (1<<14)
>> };
>>
>> +enum rat_op_flags
>> +{
>> + RF_RTN = (1 << 0),
>> +
>> +};
>> +
>> /* ALU instruction info */
>> struct alu_op_info
>> {
>> @@ -182,6 +188,15 @@ struct cf_op_info
>> int flags;
>> };
>>
>> +/* CF RAT instruction info */
>> +struct rat_op_info
>> +{
>> + const char * name;
>> + /* 0 - EG, 1 - CM */
>> + int opcode[2];
>> + int flags;
>> +};
>> +
>> static const struct alu_op_info alu_op_table[] = {
>> {"ADD", 2, { 0x00, 0x00 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_M_COMM | AF_M_ASSOC },
>> {"MUL", 2, { 0x01, 0x01 },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_M_COMM | AF_M_ASSOC },
>> @@ -665,6 +680,97 @@ static const struct cf_op_info cf_op_table[] = {
>> {"CF_NATIVE", { 0x00, 0x00, 0x00, 0x00 }, 0 }
>> };
>>
>> +static const struct rat_op_info rat_op_table[] = {
>> + {"NOP", {0x00, 0x00}, 0},
>> + {"STORE_TYPED", {0x01, 0x01}, 0},
>> + {"STORE_RAW", {0x02, -1}, 0},
>
> The LLVM backend uses the STORE_RAW instructions on Cayman
> even though the docs don't list it is a legal instructions. Will this
> cause the code to crash?
Yes, I think it will cause assert (or crash if asserts are disabled),
though only if sbcl or sbdisasm are enabled in R600_DEBUG.
>
> I have it on my TODO list to use the STORE_* instructions on Cayman, but
> I'm not sure when I'll be able to get to it. Maybe for now you can
> enable this opcode on Cayman too.
Of course, if it works then possibly the doc is not completely correct.
On the other hand, I wonder if the doc is right and this might explain
some issues people report with compute on cayman.
Anyway I'll enable this opcode on Cayman for now to avoid the problems.
>
> -Tom
>
>> + {"STORE_RAW_FDENORM", {0x03, -1}, 0},
>> + {"CMPXCHG_INT", {0x04, 0x00}, 0},
There is a typo in cayman opcode, should be 0x04 instead of 0x00, I'll
fix it too.
Vadim
>> + {"CMPXCHG_FLT", {0x05, -1}, 0},
>> + {"CMPXCHG_FDENORM", {0x06, -1}, 0},
>> + {"ADD", {0x07, 0x07}, 0},
>> + {"SUB", {0x08, 0x08}, 0},
>> + {"RSUB", {0x09, 0x09}, 0},
>> + {"MIN_INT", {0x0A, 0x0A}, 0},
>> + {"MIN_UINT", {0x0B, 0x0B}, 0},
>> + {"MAX_INT", {0x0C, 0x0C}, 0},
>> + {"MAX_UINT", {0x0D, 0x0D}, 0},
>> + {"AND", {0x0E, 0x0E}, 0},
>> + {"OR", {0x0F, 0x0F}, 0},
>> + {"XOR", {0x10, 0x10}, 0},
>> + {"MSKOR", {0x11, -1}, 0},
>> + {"INC_UINT", {0x12, 0x12}, 0},
>> + {"DEC_UINT", {0x13, 0x13}, 0},
>> +
>> + {"STORE_DWORD", { -1, 0x14}, 0},
>> + {"STORE_SHORT", { -1, 0x15}, 0},
>> + {"STORE_BYTE", { -1, 0x16}, 0},
>> +
>> + {"NOP_RTN_INTERNAL", {0x20, 0x20}, 0},
>> +
>> + {"XCHG_RTN", {0x22, 0x22}, RF_RTN },
>> + {"XCHG_FDENORM_RTN", {0x23, -1}, RF_RTN },
>> + {"CMPXCHG_INT_RTN", {0x24, 0x24}, RF_RTN },
>> + {"CMPXCHG_FLT_RTN", {0x25, 0x25}, RF_RTN },
>> + {"CMPXCHG_FDENORM_RTN", {0x26, 0x26}, RF_RTN },
>> + {"ADD_RTN", {0x27, 0x27}, RF_RTN },
>> + {"SUB_RTN", {0x28, 0x28}, RF_RTN },
>> + {"RSUB_RTN", {0x29, 0x29}, RF_RTN },
>> + {"MIN_INT_RTN", {0x2A, 0x2A}, RF_RTN },
>> + {"MIN_UINT_RTN", {0x2B, 0x2B}, RF_RTN },
>> + {"MAX_INT_RTN", {0x2C, 0x2C}, RF_RTN },
>> + {"MAX_UINT_RTN", {0x2D, 0x2D}, RF_RTN },
>> + {"AND_RTN", {0x2E, 0x2E}, RF_RTN },
>> + {"OR_RTN", {0x2F, 0x2F}, RF_RTN },
>> + {"XOR_RTN", {0x30, 0x30}, RF_RTN },
>> + {"MSKOR_RTN", {0x31, -1}, RF_RTN },
>> + {"INC_UINT_RTN", {0x32, 0x32}, RF_RTN },
>> + {"DEC_UINT_RTN", {0x33, 0x33}, RF_RTN },
>> +};
>> +
>> +#define RAT_OP_NOP 0
>> +#define RAT_OP_STORE_TYPED 1
>> +#define RAT_OP_STORE_RAW 2
>> +#define RAT_OP_STORE_RAW_FDENORM 3
>> +#define RAT_OP_CMPXCHG_INT 4
>> +#define RAT_OP_CMPXCHG_FLT 5
>> +#define RAT_OP_CMPXCHG_FDENORM 6
>> +#define RAT_OP_ADD 7
>> +#define RAT_OP_SUB 8
>> +#define RAT_OP_RSUB 9
>> +#define RAT_OP_MIN_INT 10
>> +#define RAT_OP_MIN_UINT 11
>> +#define RAT_OP_MAX_INT 12
>> +#define RAT_OP_MAX_UINT 13
>> +#define RAT_OP_AND 14
>> +#define RAT_OP_OR 15
>> +#define RAT_OP_XOR 16
>> +#define RAT_OP_MSKOR 17
>> +#define RAT_OP_INC_UINT 18
>> +#define RAT_OP_DEC_UINT 19
>> +#define RAT_OP_STORE_DWORD 20
>> +#define RAT_OP_STORE_SHORT 21
>> +#define RAT_OP_STORE_BYTE 22
>> +#define RAT_OP_NOP_RTN_INTERNAL 23
>> +#define RAT_OP_XCHG_RTN 24
>> +#define RAT_OP_XCHG_FDENORM_RTN 25
>> +#define RAT_OP_CMPXCHG_INT_RTN 26
>> +#define RAT_OP_CMPXCHG_FLT_RTN 27
>> +#define RAT_OP_CMPXCHG_FDENORM_RTN 28
>> +#define RAT_OP_ADD_RTN 29
>> +#define RAT_OP_SUB_RTN 30
>> +#define RAT_OP_RSUB_RTN 31
>> +#define RAT_OP_MIN_INT_RTN 32
>> +#define RAT_OP_MIN_UINT_RTN 33
>> +#define RAT_OP_MAX_INT_RTN 34
>> +#define RAT_OP_MAX_UINT_RTN 35
>> +#define RAT_OP_AND_RTN 36
>> +#define RAT_OP_OR_RTN 37
>> +#define RAT_OP_XOR_RTN 38
>> +#define RAT_OP_MSKOR_RTN 39
>> +#define RAT_OP_INC_UINT_RTN 40
>> +#define RAT_OP_DEC_UINT_RTN 41
>> +
>>
>> #define ALU_OP2_ADD 0
>> #define ALU_OP2_MUL 1
>> @@ -1143,6 +1249,7 @@ struct r600_isa {
>> unsigned *alu_op3_map;
>> unsigned *fetch_map;
>> unsigned *cf_map;
>> + unsigned *rat_map;
>> };
>>
>> struct r600_context;
>> @@ -1170,6 +1277,12 @@ r600_isa_cf(unsigned op) {
>> return &cf_op_table[op];
>> }
>>
>> +static inline const struct rat_op_info *
>> +r600_isa_rat(unsigned op) {
>> + assert (op < TABLE_SIZE(rat_op_table));
>> + return &rat_op_table[op];
>> +}
>> +
>> static inline unsigned
>> r600_isa_alu_opcode(enum r600_chip_class chip_class, unsigned op) {
>> int opc = r600_isa_alu(op)->opcode[chip_class >> 1];
>> @@ -1199,6 +1312,15 @@ r600_isa_cf_opcode(enum r600_chip_class chip_class, unsigned op) {
>> }
>>
>> static inline unsigned
>> +r600_isa_rat_opcode(enum r600_chip_class chip_class, unsigned op) {
>> + int opc;
>> + assert(chip_class >= ISA_CC_EVERGREEN);
>> + opc = r600_isa_cf(op)->opcode[chip_class - ISA_CC_EVERGREEN];
>> + assert(opc != -1);
>> + return opc;
>> +}
>> +
>> +static inline unsigned
>> r600_isa_alu_by_opcode(struct r600_isa* isa, unsigned opcode, unsigned is_op3) {
>> unsigned op;
>> if (is_op3) {
>> @@ -1222,6 +1344,16 @@ r600_isa_fetch_by_opcode(struct r600_isa* isa, unsigned opcode) {
>> }
>>
>> static inline unsigned
>> +r600_isa_rat_by_opcode(struct r600_isa* isa, unsigned opcode) {
>> + unsigned op;
>> + assert(isa->rat_map);
>> + op = isa->rat_map[opcode];
>> + assert(op);
>> + return op - 1;
>> +}
>> +
>> +
>> +static inline unsigned
>> r600_isa_cf_by_opcode(struct r600_isa* isa, unsigned opcode, unsigned is_alu) {
>> unsigned op;
>> assert(isa->cf_map);
>> --
>> 1.8.2.1
>>
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