[PATCH] Radeon 5/11 : Fix BIOS dividers with MergedFB

[Benjamin Herrenschmidt]

When using MergedFB, the driver would call RADEONInitPLLRegisters for the first
head even when UseBiosDividers was set to TRUE, which was incorrect. This patch
fixes it by moving the test of UseBiosDividers into RADEONInitPLLRegisters which
simplifies the code in the caller and is more logical.

Index: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_driver.c
===================================================================
--- xc.orig/programs/Xserver/hw/xfree86/drivers/ati/radeon_driver.c	2004-12-05 20:16:30.611394376 +1100
+++ xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_driver.c	2004-12-05 20:20:56.901912064 +1100
@@ -6975,8 +6975,8 @@
 }
 
 /* Define PLL registers for requested video mode */
-static void RADEONInitPLLRegisters(RADEONSavePtr save, RADEONPLLPtr pll,
-				   double dot_clock)
+static void RADEONInitPLLRegisters(RADEONInfoPtr info, RADEONSavePtr save,
+				   RADEONPLLPtr pll, double dot_clock)
 {
     unsigned long  freq = dot_clock * 100;
 
@@ -7000,6 +7000,13 @@
 	{  0, 0 }
     };
 
+    if (info->UseBiosDividers) {
+	save->ppll_ref_div = info->RefDivider;
+	save->ppll_div_3   = info->FeedbackDivider | (info->PostDivider << 16);
+	save->htotal_cntl  = 0;
+	return;    
+    }
+
     if (freq > pll->max_pll_freq)      freq = pll->max_pll_freq;
     if (freq * 12 < pll->min_pll_freq) freq = pll->min_pll_freq / 12;
 
@@ -7169,7 +7176,7 @@
             return FALSE;
         dot_clock = (((RADEONMergedDisplayModePtr)mode->Private)->CRT1)->Clock / 1000.0;
         if (dot_clock) {
-            RADEONInitPLLRegisters(save, &info->pll, dot_clock);
+            RADEONInitPLLRegisters(info->save, &info->pll, dot_clock);
         } else {
             save->ppll_ref_div = info->SavedReg.ppll_ref_div;
             save->ppll_div_3   = info->SavedReg.ppll_div_3;
@@ -7184,13 +7191,7 @@
 	    return FALSE;
 	dot_clock = mode->Clock/1000.0;
 	if (dot_clock) {
-            if (info->UseBiosDividers) {
-                save->ppll_ref_div = info->RefDivider;
-                save->ppll_div_3   = info->FeedbackDivider | (info->PostDivider << 16);
-                save->htotal_cntl  = 0;
-            }
-            else
-		RADEONInitPLLRegisters(save, &info->pll, dot_clock);
+	    RADEONInitPLLRegisters(info, save, &info->pll, dot_clock);
 	} else {
 	    save->ppll_ref_div = info->SavedReg.ppll_ref_div;
 	    save->ppll_div_3   = info->SavedReg.ppll_div_3;