ColorTiling breaks output on G5

[Roland Scheidegger]

Andreas wrote:
> Hi,
> 
> 
>>This might not actually be a problem with endianness (could be), but
>>with color tiling on r300. It should work on r200 and r100 chip
>>families, but it could well fail on r300. In fact that it's enabled on
>>r300 is an accident (I forgot to disable it on these chips when I
>>decided to enable it by default).
> 
> 
> I am not sure if it helps but my computer (x86) uses a FireGL T2 chip and I 
> have to turn the color tiling off. If I don't, it produces the aforementioned 
> stripes.
> 
> 
>>There could be mostly two problems why it wouldn't work on r300 I think,
>>either the surface info regs might need to be set up differently (they
>>need different setup for r100 and r200 too so that wouldn't be
>>surprising), or the blitter needs to be configured differently when
>>uploading data (this one is the same for r100 and r200 though). Of
>>course it could be both...
> 
> 
> If you have patches to test any of the possibilities I would try them if you 
> like.

Hmm ok. Color tiling just is broken on r300 then. Well it wouldn't 
really do anything useful currently anyway, so this patch should fix 
that (just always disables color tiling on new chips). I'll check that 
in if it works.
Someone with docs (or too much time for reverse-engeneering...) would 
need to fix that later if the experimental r300 dri driver is going to 
support tiling for a performance boost.

Roland
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