Request for Intel 915 hw information

[Jesse Barnes]

On Friday, September 21, 2007 7:55:14 am Krzysztof Halasa wrote:
> Jesse Barnes <jbarnes at virtuousgeek.org> writes:
> > Err yes, that's what I meant.  However, there are separate bits in the
> > PIPE*STAT registers for controlling whether you get vblank interrupts
> > on even or odd frames or both.
> >
> > The odd event enable bit is 21 and even is 20.  They shouldn't be on
> > unless an interlaced mode is active.
>
> Well, it doesn't seem to work at the moment. I have set bit 20 or 21
> and I'm still getting IRQs every field. Perhaps I should ACK the IRQ
> field event somehow?
>
> Is there a specific way, order etc. I should set the bits?
>
> I noticed other bits in PIPEASTAT are changed by the chip itself.
> They seem to be "write 1 to clear" status bits type and they seem
> to indicate the field. I'm getting (after some time) value 0x233 so
> they are (at least) bits 0, 1, 4, 5 and 9.

Yeah, they're part of the interrupt handling design.  I'm surprised we don't 
have them all documented in headers yet (sorry I just told you about the 
enable bits last time, and not the status bits), here's the whole list:

#define PIPEASTAT 0x70024
#define PIPEBSTAT 0x71024

/*
 * Bits 16-31 control whether a given event is enabled.
 * Bits 0-15 give actual status.
 *
 * Before clearing the appropriate bit in IIR on interrupt
 * receipt, write a '1' to the corresponding field (in bits
 * 0-15) first to prevent spurious interrupts.
 */
#define   PIPESTAT_FIFO_UNDERRUN	(1 << 31)
          /* 30 rsvd, mbz */
#define   PIPESTAT_CRC_ERROR_EN		(1 << 29)
#define   PIPESTAT_CRC_DONE_EN		(1 << 28)
          /* 27 rsvd, mbz */
#define   PIPESTAT_HOTPLUG_EN		(1 << 26)
#define   PIPESTAT_VERTICAL_SYNC_EN	(1 << 25)
#define   PIPESTAT_DISPLINE_COMP_EN	(1 << 24)
          /* 23-22 rsvd, mbz */
#define   PIPESTAT_FLD_EVT_ODD_EN	(1 << 21)
#define   PIPESTAT_FLD_EVT_EVEN_EN	(1 << 20)
          /* 19 rsvd, mbz */
#define   PIPESTAT_TV_HOTPLUG_EN	(1 << 18)
#define   PIPESTAT_VBLANK_EN		(1 << 17)
#define   PIPESTAT_OVL_UPDATE_EN	(1 << 16)
#define   PIPESTAT_HOTPLUG_STATE	(1 << 15)
          /* 14 rsvd, mbz */
#define   PIPESTAT_CRC_ERROR		(1 << 13)
#define   PIPESTAT_CRC_DONE		(1 << 12)
          /* 11 rsvd, mbz */
#define   PIPESTAT_HOTPLUG		(1 << 10)
#define   PIPESTAT_VSYNC		(1 << 9)
#define   PIPESTAT_DISPLINE_COMP	(1 << 8)
          /* 7-6 rsvd, mbz */
#define   PIPESTAT_FLD_EVT_ODD		(1 << 5)
#define   PIPESTAT_FLD_EVT_EVEN		(1 << 4)
          /* 3 rsvd, mbz */
#define   PIPESTAT_TV_HOTPLUG		(1 << 2)
#define   PIPESTAT_VBLANK		(1 << 1)
#define   PIPESTAT_OVL_UPDATE		(1 << 0)

> Is it like that on all i830 and later, so I can put it in the code
> unconditionally?

I think generations prior to i915 don't have the full 32 bit scheme, but I 
don't have the docs handy to be sure (at least the i815 docs are public and 
they only describe a 16 bit interrupt scheme).

Hopefully the pipe status bits are enough.  It sounds like you're getting the 
right field events, though less conveniently than you'd like...

Jesse