[Beignet] [PATCH 04/10 OpenCL-2.0] Correct the register order and wellform of WorkGroupInstruction.

[junyan.he at inbox.com]

From: Junyan He <junyan.he at linux.intel.com>

Signed-off-by: Junyan He <junyan.he at linux.intel.com>
---
 backend/src/ir/instruction.cpp        |    3 ++-
 backend/src/llvm/llvm_gen_backend.cpp |    6 +++---
 2 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/backend/src/ir/instruction.cpp b/backend/src/ir/instruction.cpp
index 02498bc..6b9207e 100644
--- a/backend/src/ir/instruction.cpp
+++ b/backend/src/ir/instruction.cpp
@@ -1161,6 +1161,7 @@ namespace ir {
       switch (this->workGroupOp) {
         case WORKGROUP_OP_ANY:
         case WORKGROUP_OP_ALL:
+          break;
         case WORKGROUP_OP_REDUCE_ADD:
         case WORKGROUP_OP_REDUCE_MIN:
         case WORKGROUP_OP_REDUCE_MAX:
@@ -1170,7 +1171,7 @@ namespace ir {
         case WORKGROUP_OP_EXCLUSIVE_ADD:
         case WORKGROUP_OP_EXCLUSIVE_MIN:
         case WORKGROUP_OP_EXCLUSIVE_MAX:
-          if (this->srcNum != 1) {
+          if (this->srcNum != 3) {
             whyNot = "Wrong number of source.";
             return false;
           }
diff --git a/backend/src/llvm/llvm_gen_backend.cpp b/backend/src/llvm/llvm_gen_backend.cpp
index 47a9a63..83c1b96 100644
--- a/backend/src/llvm/llvm_gen_backend.cpp
+++ b/backend/src/llvm/llvm_gen_backend.cpp
@@ -2898,9 +2898,9 @@ namespace gbe
           getType(ctx, (*AI)->getType()));
     } else {
       ir::Register src[3];
-      src[0] = ir::ocl::threadn;
-      src[1] = ir::ocl::threadid;
-      src[2] = this->getRegister(*(AI++));
+      src[0] = this->getRegister(*(AI++));
+      src[1] = ir::ocl::threadn;
+      src[2] = ir::ocl::threadid;
       const ir::Tuple srcTuple = ctx.arrayTuple(&src[0], 3);
       ctx.WORKGROUP(opcode, (uint32_t)tidMapSLM, getRegister(&I), srcTuple, 3, getType(ctx, (*AI)->getType()));
     }
-- 
1.7.9.5