[PATCH v2] drm/panel: boe-tv101wum-nl6: Completely pull GPW to VGL before TP term

neil.armstrong at linaro.org neil.armstrong at linaro.org
Mon Oct 9 08:57:05 UTC 2023


On 07/10/2023 08:49, Ruihai Zhou wrote:
> The sta_himax83102 panel sometimes shows abnormally flickering
> horizontal lines. The front gate output will precharge the X point of
> the next pole circuit before TP(TouchPanel Enable) term starts, and wait
> until the end of the TP term to resume the CLK. For this reason, the X
> point must be maintained during the TP term. In abnormal case, we
> measured a slight leakage at point X. This because during the TP term,
> the GPW does not fully pull the VGL low, causing the TFT to not be
> closed tightly.
> 
> To fix this, we completely pull GPW to VGL before entering the TP term.
> This will ensure that the TFT is closed tightly and prevent the abnormal
> display.
> 
> Fixes: 1bc2ef065f13 ("drm/panel: Support for Starry-himax83102-j02 TDDI MIPI-DSI panel")
> Signed-off-by: Ruihai Zhou <zhouruihai at huaqin.corp-partner.google.com>
> ---
> Changes since v1:
> 
> - Rebased on top of drm-misc-next
> - Add Fixes tag from Jessica's comment
> 
> v1: https://patchwork.kernel.org/project/dri-devel/patch/20230912105932.16618-1-zhouruihai@huaqin.corp-partner.google.com/
> ---
>   drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c | 4 +---
>   1 file changed, 1 insertion(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
> index 5ac926281d2c..c9087f474cbc 100644
> --- a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
> +++ b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
> @@ -1342,9 +1342,7 @@ static const struct panel_init_cmd starry_himax83102_j02_init_cmd[] = {
>   	_INIT_DCS_CMD(0xB1, 0x01, 0xBF, 0x11),
>   	_INIT_DCS_CMD(0xCB, 0x86),
>   	_INIT_DCS_CMD(0xD2, 0x3C, 0xFA),
> -	_INIT_DCS_CMD(0xE9, 0xC5),
> -	_INIT_DCS_CMD(0xD3, 0x00, 0x00, 0x00, 0x00, 0x80, 0x0C, 0x01),
> -	_INIT_DCS_CMD(0xE9, 0x3F),
> +	_INIT_DCS_CMD(0xD3, 0x00, 0x00, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x0C, 0x01),
>   	_INIT_DCS_CMD(0xE7, 0x02, 0x00, 0x28, 0x01, 0x7E, 0x0F, 0x7E, 0x10, 0xA0, 0x00, 0x00, 0x20, 0x40, 0x50, 0x40),
>   	_INIT_DCS_CMD(0xBD, 0x02),
>   	_INIT_DCS_CMD(0xD8, 0xFF, 0xFF, 0xBF, 0xFE, 0xAA, 0xA0, 0xFF, 0xFF, 0xBF, 0xFE, 0xAA, 0xA0),

Reviewed-by: Neil Armstrong <neil.armstrong at linaro.org>


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