[Intel-gfx] [PATCH 1/3] drm/i915: implement new pm ops for i915

Zhenyu Wang zhenyuw at linux.intel.com
Wed Dec 16 06:36:10 CET 2009


On 2009.12.02 09:36:48 -0800, Jesse Barnes wrote:
> 
> > On 2009.11.25 13:09:37 +0800, Zhenyu Wang wrote:
> > > One problem in i915 hibernate with current legacy pci pm ops is
> > > that after we do freeze, we'll be forced to do resume once again,
> > > which re-init some resources and do modesetting again, that is
> > > unnecessary for hibernate. This patch trys to bypass that.
> > > 
> > > We can't resolve this within legacy pm framework, but can do it
> > > easily with new pm ops. Suspend (S3) process has also been kept
> > > without change.
> > 
> > Any comment or concern about this one?
> > 
> > This patch only changes for hibernate (S4), and removes screen
> > flicking (extra modesetting) during hibernate before power off
> > machine. If any other device failed in the hibernate process, the
> > driver for it should be fixed and worst case is a VT switch to bring
> > back X.
> 
> Yeah sorry meant to look at this but it got lost.  It looks ok, the
> core DRM should probably be converted too.  I had some patches for that
> awhile back but I think the interfaces have changed since then...
> 

Looks it should be specified by driver in KMS case as always true now.
Updated one below.

From 2caaf2f129ff1176c2aef9c7e8ad3ed04d529329 Mon Sep 17 00:00:00 2001
From: Zhenyu Wang <zhenyuw at linux.intel.com>
Date: Wed, 16 Dec 2009 13:30:34 +0800
Subject: [PATCH] drm/i915: implement new pm ops for i915

One problem in i915 hibernate with current legacy pci pm ops is
that after we do freeze, we'll be forced to do resume once again,
which re-init some resources and do modesetting again, that is
unnecessary for hibernate. This patch trys to bypass that.

We can't resolve this within legacy pm framework, but can do it
easily with new pm ops. Suspend (S3) process has also been kept
without change.

Signed-off-by: Zhenyu Wang <zhenyuw at linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c |   53 ++++++++++++++++++++++++++++++++++----
 1 files changed, 47 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 2fa2178..6978a22 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -284,6 +284,52 @@ i915_pci_resume(struct pci_dev *pdev)
 	return i915_resume(dev);
 }
 
+static int
+i915_pm_suspend(struct device *dev)
+{
+	return i915_pci_suspend(to_pci_dev(dev), PMSG_SUSPEND);
+}
+
+static int
+i915_pm_resume(struct device *dev)
+{
+	return i915_pci_resume(to_pci_dev(dev));
+}
+
+static int
+i915_pm_freeze(struct device *dev)
+{
+	return i915_pci_suspend(to_pci_dev(dev), PMSG_FREEZE);
+}
+
+static int
+i915_pm_thaw(struct device *dev)
+{
+	/* thaw during hibernate, do nothing! */
+	return 0;
+}
+
+static int
+i915_pm_poweroff(struct device *dev)
+{
+	return i915_pci_suspend(to_pci_dev(dev), PMSG_HIBERNATE);
+}
+
+static int
+i915_pm_restore(struct device *dev)
+{
+	return i915_pci_resume(to_pci_dev(dev));
+}
+
+const struct dev_pm_ops i915_pm_ops = {
+     .suspend = i915_pm_suspend,
+     .resume = i915_pm_resume,
+     .freeze = i915_pm_freeze,
+     .thaw = i915_pm_thaw,
+     .poweroff = i915_pm_poweroff,
+     .restore = i915_pm_restore,
+};
+
 static struct vm_operations_struct i915_gem_vm_ops = {
 	.fault = i915_gem_fault,
 	.open = drm_gem_vm_open,
@@ -303,8 +349,6 @@ static struct drm_driver driver = {
 	.lastclose = i915_driver_lastclose,
 	.preclose = i915_driver_preclose,
 	.postclose = i915_driver_postclose,
-	.suspend = i915_suspend,
-	.resume = i915_resume,
 	.device_is_agp = i915_driver_device_is_agp,
 	.enable_vblank = i915_enable_vblank,
 	.disable_vblank = i915_disable_vblank,
@@ -344,10 +388,7 @@ static struct drm_driver driver = {
 		 .id_table = pciidlist,
 		 .probe = i915_pci_probe,
 		 .remove = i915_pci_remove,
-#ifdef CONFIG_PM
-		 .resume = i915_pci_resume,
-		 .suspend = i915_pci_suspend,
-#endif
+		 .driver.pm = &i915_pm_ops,
 	},
 
 	.name = DRIVER_NAME,
-- 
1.6.3.3

-- 
Open Source Technology Center, Intel ltd.

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