[Intel-gfx] [PATCH 0/2]drm/i915: Find best PLL timing to obtain stable image on G4X platform(V3)
ling.ma at intel.com
Wed Mar 18 05:13:19 PDT 2009
Our clock is generated by parameters- n, m1, m2, p1, p2. However for
different platforms we need corresponding setting parameters so that
clock derived from them matches hardware requirement. The patch intends
to provide precise parameters specified in reference spreadsheet.
It has fixed bug #17805 and #17508.
Any comments are welcome.
[PATCH 1/2]drm/i915: Define documented PLL timing limits for G4X
[PATCH 2/2]drm/i915: Generate precise PLL timing parameters according to
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