[Intel-gfx] [PATCH 13/24] drm/i915: handle DDI-related assertions

[Jesse Barnes]

On Thu, 26 Apr 2012 15:21:08 -0300
Eugeni Dodonov <eugeni.dodonov at intel.com> wrote:

> Prevent bogus asserts on DDI-related paths.
> 
> Signed-off-by: Eugeni Dodonov <eugeni.dodonov at intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c |   35 ++++++++++++++++++++++++----------
>  1 file changed, 25 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index ca0edbf..b2d3dc1 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -954,9 +954,16 @@ static void assert_fdi_tx(struct drm_i915_private *dev_priv,
>  	u32 val;
>  	bool cur_state;
>  
> -	reg = FDI_TX_CTL(pipe);
> -	val = I915_READ(reg);
> -	cur_state = !!(val & FDI_TX_ENABLE);
> +	if (IS_HASWELL(dev_priv->dev)) {
> +		/* On Haswell, DDI is used instead of FDI_TX_CTL */
> +		reg = DDI_FUNC_CTL(pipe);
> +		val = I915_READ(reg);
> +		cur_state = !!(val & PIPE_DDI_FUNC_ENABLE);
> +	} else {
> +		reg = FDI_TX_CTL(pipe);
> +		val = I915_READ(reg);
> +		cur_state = !!(val & FDI_TX_ENABLE);
> +	}
>  	WARN(cur_state != state,
>  	     "FDI TX state assertion failure (expected %s, current %s)\n",
>  	     state_string(state), state_string(cur_state));
> @@ -991,6 +998,10 @@ static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
>  	if (dev_priv->info->gen == 5)
>  		return;
>  
> +	/* On Haswell, DDI ports are responsible for the FDI PLL setup */
> +	if (IS_HASWELL(dev_priv->dev))
> +		return;
> +
>  	reg = FDI_TX_CTL(pipe);
>  	val = I915_READ(reg);
>  	WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
> @@ -2515,14 +2526,18 @@ static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
>  	POSTING_READ(reg);
>  	udelay(200);
>  
> -	/* Enable CPU FDI TX PLL, always on for Ironlake */
> -	reg = FDI_TX_CTL(pipe);
> -	temp = I915_READ(reg);
> -	if ((temp & FDI_TX_PLL_ENABLE) == 0) {
> -		I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
> +	/* On Haswell, the PLL configuration for ports and pipes is handled
> +	 * separately, as part of DDI setup */
> +	if (!IS_HASWELL(dev)) {
> +		/* Enable CPU FDI TX PLL, always on for Ironlake */
> +		reg = FDI_TX_CTL(pipe);
> +		temp = I915_READ(reg);
> +		if ((temp & FDI_TX_PLL_ENABLE) == 0) {
> +			I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
>  
> -		POSTING_READ(reg);
> -		udelay(100);
> +			POSTING_READ(reg);
> +			udelay(100);
> +		}
>  	}
>  }
>  

Maybe some small helper functions instead?  Or possibly separate high
level enable/disable functions...

-- 
Jesse Barnes, Intel Open Source Technology Center