[Intel-gfx] [PATCH] drm/i915: Always update RPS interrupts thresholds along with frequency

Daniel Vetter daniel at ffwll.ch
Tue May 22 20:56:55 CEST 2012


On Sat, Apr 28, 2012 at 07:18:30PM -0700, Ben Widawsky wrote:
> On Sat, 28 Apr 2012 08:56:39 +0100
> Chris Wilson <chris at chris-wilson.co.uk> wrote:
> 
> > In order to avoid missed down-interrupts when coming out of RC6, it is
> > advised that we always reset the down-threshold upon a PM event. This
> > is due to that the PM unit goes through a little dance when coming
> > out of RC6, it first brings the GPU up at the lowest frequency then a
> > short time later it restores the thresholds. During that interval, the
> > down-interval may expire and the interrupt be suppressed.
> > 
> > Now aware of the dance taking place within the GPU when coming out of
> > RC6, one wonders what other writes need to be queued in the fifo
> > buffer in order to be properly sequenced; setting the RP state
> > appears to be one.
> > 
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=44006
> > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> 
> I tried really hard to review this, but it was too much. The code
> definitely is cleaner as a result, so this is:
> Acked-by: Ben Widawsky <ben at bwidawsk.net>
Picked up for -fixes with Jesse's irc r-b added, thanks for the patch.
-Daniel
-- 
Daniel Vetter
Mail: daniel at ffwll.ch
Mobile: +41 (0)79 365 57 48



More information about the Intel-gfx mailing list