[Intel-gfx] [PATCH 1/3] drm/i915: disable RCBP and VDS unit clock gating on IVB and VLV

[Daniel Vetter]

On Tue, May 22, 2012 at 03:15:53PM -0700, Jesse Barnes wrote:
> The RCBP workaround still applies on these chips, and we need VDS as well.
> 
> References: https://bugs.freedesktop.org/show_bug.cgi?id=50251
> Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org>

- Looks like the driver boot fetch enable wa crept into this patch.
- You kill the comment for RCZUNIT wa with the canonical wa name from vpg
  for that.
- VDSUNIT doesn't have a comment, just looks odd given that the others
  have/had one.
- I think it'd be good if we mention the canonical wa name/tag from vpg
  (at least in the commit message), especially if there's no Bspec
  reference. Otherwise we won't ever find this stuff again in the wa
  database.
- At least the driver boot fetch exist in Bspec. Generally for workarounds
  I want a Bspec reference (if it exists), any other references from vpg
  or failing that (for something we've invented ourselves).

Cheers, Daniel

> ---
>  drivers/gpu/drm/i915/i915_reg.h |    1 +
>  drivers/gpu/drm/i915/intel_pm.c |   52 +++++++++++++++++++++++++++++++-------
>  2 files changed, 43 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0f45a18..e479e1a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3989,6 +3989,7 @@
>  # define GEN6_CSUNIT_CLOCK_GATE_DISABLE			(1 << 7)
>  
>  #define GEN6_UCGCTL2				0x9404
> +# define GEN7_VDSUNIT_CLOCK_GATE_DISABLE		(1 << 30)
>  # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE		(1 << 13)
>  # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE		(1 << 12)
>  # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE		(1 << 11)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index fe04be6..4c95e50 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3334,6 +3334,9 @@ static void gen6_init_clock_gating(struct drm_device *dev)
>  		   ILK_DPARB_CLK_GATE  |
>  		   ILK_DPFD_CLK_GATE);
>  
> +	I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
> +		   GEN6_MBCTL_ENABLE_BOOT_FETCH);
> +
>  	for_each_pipe(pipe) {
>  		I915_WRITE(DSPCNTR(pipe),
>  			   I915_READ(DSPCNTR(pipe)) |
> @@ -3366,11 +3369,6 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
>  	I915_WRITE(WM2_LP_ILK, 0);
>  	I915_WRITE(WM1_LP_ILK, 0);
>  
> -	/* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
> -	 * This implements the WaDisableRCZUnitClockGating workaround.
> -	 */
> -	I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
> -
>  	I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
>  
>  	I915_WRITE(IVB_CHICKEN3,
> @@ -3387,6 +3385,22 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
>  	I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
>  			GEN7_WA_L3_CHICKEN_MODE);
>  
> +	/* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
> +	 * gating disable must be set.  Failure to set it results in
> +	 * flickering pixels due to Z write ordering failures after
> +	 * some amount of runtime in the Mesa "fire" demo, and Unigine
> +	 * Sanctuary and Tropics, and apparently anything else with
> +	 * alpha test or pixel discard.
> +	 *
> +	 * According to the spec, bit 11 (RCCUNIT) must also be set,
> +	 * but we didn't debug actual testcases to find it out.
> +	 */
> +	I915_WRITE(GEN6_UCGCTL2,
> +		   GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
> +		   GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
> +		   GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
> +		   GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
> +
>  	/* This is required by WaCatErrorRejectionIssue */
>  	I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
>  			I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
> @@ -3399,6 +3413,9 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
>  		intel_flush_display_plane(dev_priv, pipe);
>  	}
>  
> +	I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
> +		   GEN6_MBCTL_ENABLE_BOOT_FETCH);
> +
>  	gen7_setup_fixed_func_scheduler(dev_priv);
>  
>  	/* WaDisable4x2SubspanOptimization */
> @@ -3418,11 +3435,6 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
>  	I915_WRITE(WM2_LP_ILK, 0);
>  	I915_WRITE(WM1_LP_ILK, 0);
>  
> -	/* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
> -	 * This implements the WaDisableRCZUnitClockGating workaround.
> -	 */
> -	I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
> -
>  	I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
>  
>  	I915_WRITE(IVB_CHICKEN3,
> @@ -3442,6 +3454,26 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
>  		   I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
>  		   GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
>  
> +	I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
> +		   GEN6_MBCTL_ENABLE_BOOT_FETCH);
> +
> +
> +	/* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
> +	 * gating disable must be set.  Failure to set it results in
> +	 * flickering pixels due to Z write ordering failures after
> +	 * some amount of runtime in the Mesa "fire" demo, and Unigine
> +	 * Sanctuary and Tropics, and apparently anything else with
> +	 * alpha test or pixel discard.
> +	 *
> +	 * According to the spec, bit 11 (RCCUNIT) must also be set,
> +	 * but we didn't debug actual testcases to find it out.
> +	 */
> +	I915_WRITE(GEN6_UCGCTL2,
> +		   GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
> +		   GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
> +		   GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
> +		   GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
> +
>  	for_each_pipe(pipe) {
>  		I915_WRITE(DSPCNTR(pipe),
>  			   I915_READ(DSPCNTR(pipe)) |
> -- 
> 1.7.5.4
> 
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-- 
Daniel Vetter
Mail: daniel at ffwll.ch
Mobile: +41 (0)79 365 57 48