[Intel-gfx] [PATCH 07/11] drm/i915: disable DIP while changing the port

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni at intel.com>

The register specification says we need to do this.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
---
 drivers/gpu/drm/i915/intel_hdmi.c |   30 +++++++++++++++++++++++-------
 1 file changed, 23 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index ce68ec0..5bcd609 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -309,6 +309,7 @@ void g4x_set_infoframes(struct drm_encoder *encoder,
 	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 	u32 reg = VIDEO_DIP_CTL;
 	u32 val = I915_READ(reg);
+	u32 port;
 
 	if (!intel_hdmi->has_hdmi_sink) {
 		/* If the registers were not initialized yet, they might be
@@ -329,18 +330,25 @@ void g4x_set_infoframes(struct drm_encoder *encoder,
 		return;
 	}
 
-	val &= ~VIDEO_DIP_PORT_MASK;
 	switch (intel_hdmi->sdvox_reg) {
 	case SDVOB:
-		val |= VIDEO_DIP_PORT_B;
+		port = VIDEO_DIP_PORT_B;
 		break;
 	case SDVOC:
-		val |= VIDEO_DIP_PORT_C;
+		port = VIDEO_DIP_PORT_C;
 		break;
 	default:
 		return;
 	}
 
+	if (port != (val & VIDEO_DIP_PORT_MASK)) {
+		val &= ~VIDEO_DIP_ENABLE;
+		val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
+		I915_WRITE(reg, val);
+		val &= ~VIDEO_DIP_PORT_MASK;
+		val |= port;
+	}
+
 	val |= VIDEO_DIP_ENABLE;
 	val &= ~VIDEO_DIP_ENABLE_VENDOR;
 
@@ -358,6 +366,7 @@ void ibx_set_infoframes(struct drm_encoder *encoder,
 	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 	u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 	u32 val = I915_READ(reg);
+	u32 port;
 
 	if (!intel_hdmi->has_hdmi_sink) {
 		/* See the big comment in g4x_set_infoframes() */
@@ -369,21 +378,28 @@ void ibx_set_infoframes(struct drm_encoder *encoder,
 		return;
 	}
 
-	val &= ~VIDEO_DIP_PORT_MASK;
 	switch (intel_hdmi->sdvox_reg) {
 	case HDMIB:
-		val |= VIDEO_DIP_PORT_B;
+		port = VIDEO_DIP_PORT_B;
 		break;
 	case HDMIC:
-		val |= VIDEO_DIP_PORT_C;
+		port = VIDEO_DIP_PORT_C;
 		break;
 	case HDMID:
-		val |= VIDEO_DIP_PORT_D;
+		port = VIDEO_DIP_PORT_D;
 		break;
 	default:
 		return;
 	}
 
+	if (port != (val & VIDEO_DIP_PORT_MASK)) {
+		val &= ~VIDEO_DIP_ENABLE;
+		val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
+		I915_WRITE(reg, val);
+		val &= ~VIDEO_DIP_PORT_MASK;
+		val |= port;
+	}
+
 	val |= VIDEO_DIP_ENABLE;
 	val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 		 VIDEO_DIP_ENABLE_GCP);
-- 
1.7.10