[Intel-gfx] [PATCH 5/9] drm/i915: Include display_mmio_offset in sequencer index/data registers

[Daniel Vetter]

On Fri, Jan 25, 2013 at 09:44:45PM +0200, ville.syrjala at linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> SR01 needs to be touched to disable VGA on non-UMS setups too.
> So the sequencer registers need to include the appripriate offset
> on VLV.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

I've applied patches up to this one. The vga_cntrl one needs the
safe/restore patches applied first, which is awaiting a bit of review. And
I think before I merge the patch to finally kill IS_DISPLAYREG a few days
of testing would be good.

Thanks for doing this.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch