[Intel-gfx] [PATCH v2 3/3] drm/i915/icl+: Always use TPS2 or TPS3 when exiting PSR

[kbuild test robot]

Hi José,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on v5.0 next-20190305]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Jos-Roberto-de-Souza/drm-i915-vbt-Parse-and-use-the-new-field-with-PSR2-TP2-3-wakeup-time/20190306-140524
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-randconfig-x006-201909 (attached as .config)
compiler: gcc-8 (Debian 8.3.0-2) 8.3.0
reproduce:
        # save the attached .config to linux build tree
        make ARCH=i386 

All errors (new ones prefixed by >>):

   drivers/gpu/drm/i915/intel_psr.c: In function 'psr1_tps_regs_val_get':
>> drivers/gpu/drm/i915/intel_psr.c:446:2: error: expected ';' before 'if'
     if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0)
     ^~

vim +446 drivers/gpu/drm/i915/intel_psr.c

0bc12bcb1 Rodrigo Vivi          2014-11-14  437  
a5f924097 José Roberto de Souza 2019-03-05  438  static u32 psr1_tps_regs_val_get(struct intel_dp *intel_dp)
0bc12bcb1 Rodrigo Vivi          2014-11-14  439  {
1895759ee Rodrigo Vivi          2018-08-27  440  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
a5f924097 José Roberto de Souza 2019-03-05  441  	u32 val = 0;
60e5ffe32 Rodrigo Vivi          2016-02-01  442  
715dd286b José Roberto de Souza 2019-03-05  443  	if (INTEL_GEN(dev_priv) >= 11)
715dd286b José Roberto de Souza 2019-03-05  444  		val |= EDP_PSR_TP4_TIME_0US
715dd286b José Roberto de Souza 2019-03-05  445  
77312ae8f Vathsala Nagaraju     2018-05-22 @446  	if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0)
77312ae8f Vathsala Nagaraju     2018-05-22  447  		val |= EDP_PSR_TP1_TIME_0us;
77312ae8f Vathsala Nagaraju     2018-05-22  448  	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100)
50db13901 Daniel Vetter         2016-05-18  449  		val |= EDP_PSR_TP1_TIME_100us;
77312ae8f Vathsala Nagaraju     2018-05-22  450  	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500)
77312ae8f Vathsala Nagaraju     2018-05-22  451  		val |= EDP_PSR_TP1_TIME_500us;
50db13901 Daniel Vetter         2016-05-18  452  	else
77312ae8f Vathsala Nagaraju     2018-05-22  453  		val |= EDP_PSR_TP1_TIME_2500us;
50db13901 Daniel Vetter         2016-05-18  454  
77312ae8f Vathsala Nagaraju     2018-05-22  455  	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0)
77312ae8f Vathsala Nagaraju     2018-05-22  456  		val |= EDP_PSR_TP2_TP3_TIME_0us;
77312ae8f Vathsala Nagaraju     2018-05-22  457  	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
50db13901 Daniel Vetter         2016-05-18  458  		val |= EDP_PSR_TP2_TP3_TIME_100us;
77312ae8f Vathsala Nagaraju     2018-05-22  459  	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
77312ae8f Vathsala Nagaraju     2018-05-22  460  		val |= EDP_PSR_TP2_TP3_TIME_500us;
50db13901 Daniel Vetter         2016-05-18  461  	else
77312ae8f Vathsala Nagaraju     2018-05-22  462  		val |= EDP_PSR_TP2_TP3_TIME_2500us;
50db13901 Daniel Vetter         2016-05-18  463  
50db13901 Daniel Vetter         2016-05-18  464  	if (intel_dp_source_supports_hbr2(intel_dp) &&
50db13901 Daniel Vetter         2016-05-18  465  	    drm_dp_tps3_supported(intel_dp->dpcd))
50db13901 Daniel Vetter         2016-05-18  466  		val |= EDP_PSR_TP1_TP3_SEL;
50db13901 Daniel Vetter         2016-05-18  467  	else
50db13901 Daniel Vetter         2016-05-18  468  		val |= EDP_PSR_TP1_TP2_SEL;
50db13901 Daniel Vetter         2016-05-18  469  
a5f924097 José Roberto de Souza 2019-03-05  470  	return val;
a5f924097 José Roberto de Souza 2019-03-05  471  }
a5f924097 José Roberto de Souza 2019-03-05  472  

:::::: The code at line 446 was first introduced by commit
:::::: 77312ae8f071fb389d9982ce743b72975990c4d9 drm/i915/psr: vbt change for psr

:::::: TO: Vathsala Nagaraju <vathsala.nagaraju at intel.com>
:::::: CC: Jani Nikula <jani.nikula at intel.com>

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation
-------------- next part --------------
A non-text attachment was scrubbed...
Name: .config.gz
Type: application/gzip
Size: 29672 bytes
Desc: not available
URL: <https://lists.freedesktop.org/archives/intel-gfx/attachments/20190306/808d687e/attachment-0001.gz>