Mesa (master): radeon/llvm: Set End of Program bit on RAT instructions

[Tom Stellard]

Module: Mesa
Branch: master
Commit: 1434a86f50e4ffc69316c7e948ebfe56a25d31da
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=1434a86f50e4ffc69316c7e948ebfe56a25d31da

Author: Tom Stellard <thomas.stellard at amd.com>
Date:   Thu Aug 23 21:51:48 2012 +0000

radeon/llvm: Set End of Program bit on RAT instructions

This code was accidently dropped during the MCCodeEmitter conversion.

---

 .../radeon/MCTargetDesc/R600MCCodeEmitter.cpp      |    2 --
 src/gallium/drivers/radeon/R600ISelLowering.cpp    |    4 +++-
 src/gallium/drivers/radeon/R600Instructions.td     |   18 +++++++++++-------
 3 files changed, 14 insertions(+), 10 deletions(-)

diff --git a/src/gallium/drivers/radeon/MCTargetDesc/R600MCCodeEmitter.cpp b/src/gallium/drivers/radeon/MCTargetDesc/R600MCCodeEmitter.cpp
index 29f1291..34c4b39 100644
--- a/src/gallium/drivers/radeon/MCTargetDesc/R600MCCodeEmitter.cpp
+++ b/src/gallium/drivers/radeon/MCTargetDesc/R600MCCodeEmitter.cpp
@@ -162,8 +162,6 @@ void R600MCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS,
     case AMDGPU::RAT_WRITE_CACHELESS_eg:
       {
         uint64_t inst = getBinaryCodeForInstr(MI, Fixups);
-        // XXX: Set End Of Program bit when necessary
-        //  inst |= (((uint64_t)1) << 53);
         EmitByte(INSTR_NATIVE, OS);
         Emit(inst, OS);
         break;
diff --git a/src/gallium/drivers/radeon/R600ISelLowering.cpp b/src/gallium/drivers/radeon/R600ISelLowering.cpp
index 376ac70..fec9d4e 100644
--- a/src/gallium/drivers/radeon/R600ISelLowering.cpp
+++ b/src/gallium/drivers/radeon/R600ISelLowering.cpp
@@ -121,6 +121,7 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
                                              &AMDGPU::R600_TReg32_XRegClass);
       unsigned ShiftValue = MRI.createVirtualRegister(
                                               &AMDGPU::R600_TReg32RegClass);
+      unsigned EOP = (llvm::next(I)->getOpcode() == AMDGPU::RETURN) ? 1 : 0;
 
       // XXX In theory, we should be able to pass ShiftValue directly to
       // the LSHR_eg instruction as an inline literal, but I tried doing it
@@ -136,7 +137,8 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
               .addReg(AMDGPU::PRED_SEL_OFF);
       BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI->getOpcode()))
               .addOperand(MI->getOperand(0))
-              .addReg(NewAddr);
+              .addReg(NewAddr)
+              .addImm(EOP); // Set End of program bit
       break;
     }
 
diff --git a/src/gallium/drivers/radeon/R600Instructions.td b/src/gallium/drivers/radeon/R600Instructions.td
index 84f839e..00c57e6 100644
--- a/src/gallium/drivers/radeon/R600Instructions.td
+++ b/src/gallium/drivers/radeon/R600Instructions.td
@@ -175,7 +175,7 @@ class EG_CF_RAT <bits <8> cf_inst, bits <6> rat_inst, bits<4> rat_id, dag outs,
   bits<4>  COMP_MASK;
   bits<4>  BURST_COUNT;
   bits<1>  VPM;
-  bits<1>  EOP;
+  bits<1>  eop;
   bits<1>  MARK;
   bits<1>  BARRIER;
 
@@ -195,7 +195,7 @@ class EG_CF_RAT <bits <8> cf_inst, bits <6> rat_inst, bits<4> rat_id, dag outs,
   let Inst{47-44} = COMP_MASK;
   let Inst{51-48} = BURST_COUNT;
   let Inst{52}    = VPM;
-  let Inst{53}    = EOP;
+  let Inst{53}    = eop;
   let Inst{61-54} = cf_inst;
   let Inst{62}    = MARK;
   let Inst{63}    = BARRIER;
@@ -921,9 +921,9 @@ let Predicates = [isEGorCayman] in {
 let usesCustomInserter = 1 in {
 
 def RAT_WRITE_CACHELESS_eg : EG_CF_RAT <0x57, 0x2, 0, (outs),
-  (ins R600_TReg32_X:$rw_gpr, R600_TReg32_X:$index_gpr),
-  "RAT_WRITE_CACHELESS_eg $rw_gpr, $index_gpr",
-  [(global_store (i32 R600_TReg32_X:$rw_gpr), R600_TReg32_X:$index_gpr)]>
+  (ins R600_TReg32_X:$rw_gpr, R600_TReg32_X:$index_gpr, i32imm:$eop),
+  "RAT_WRITE_CACHELESS_eg $rw_gpr, $index_gpr, $eop",
+  []>
 {
   let RIM         = 0;
   /* XXX: Have a separate instruction for non-indexed writes. */
@@ -935,17 +935,21 @@ def RAT_WRITE_CACHELESS_eg : EG_CF_RAT <0x57, 0x2, 0, (outs),
   let COMP_MASK   = 1;
   let BURST_COUNT = 0;
   let VPM         = 0;
-  let EOP         = 0;
   let MARK        = 0;
   let BARRIER     = 1;
 }
 
 } // End usesCustomInserter = 1
+// i32 global_store
+def : Pat <
+  (global_store (i32 R600_TReg32_X:$val), R600_TReg32_X:$ptr),
+  (RAT_WRITE_CACHELESS_eg R600_TReg32_X:$val, R600_TReg32_X:$ptr, 0)
+>;
 
 // Floating point global_store
 def : Pat <
   (global_store (f32 R600_TReg32_X:$val), R600_TReg32_X:$ptr),
-  (RAT_WRITE_CACHELESS_eg R600_TReg32_X:$val, R600_TReg32_X:$ptr)
+  (RAT_WRITE_CACHELESS_eg R600_TReg32_X:$val, R600_TReg32_X:$ptr, 0)
 >;
 
 class VTX_READ_eg <bits<8> buffer_id, dag outs, list<dag> pattern>