Mesa (8.0): i965/fs: Enable register spilling on gen7 too.

[Ian Romanick]

Module: Mesa
Branch: 8.0
Commit: 99f9c9789a2d316d97ca6791343fb697f220929e
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=99f9c9789a2d316d97ca6791343fb697f220929e

Author: Eric Anholt <eric at anholt.net>
Date:   Thu Feb  9 16:35:49 2012 -0800

i965/fs: Enable register spilling on gen7 too.

It turns out the same messages work on gen7, we were just being paranoid.

Fixes the penumbra shadows mode of Lightsmark since the register
allocation fix.

NOTE: This is a candidate for release branches.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
(cherry picked from commit 93831a54c7d4e74f353e0029164b1b3262e98806)

---

 src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp |    2 --
 1 files changed, 0 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
index 0d1712e..7da1418 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
@@ -236,8 +236,6 @@ fs_visitor::assign_regs()
 
       if (reg == -1) {
 	 fail("no register to spill\n");
-      } else if (intel->gen >= 7) {
-	 fail("no spilling support on gen7 yet\n");
       } else if (c->dispatch_width == 16) {
 	 fail("no spilling support on 16-wide yet\n");
       } else {