Mesa (master): i965: Use the new brw_load_register_mem helper for draw indirect.

[Kenneth Graunke]

Module: Mesa
Branch: master
Commit: e990234ff6fd0f8d393cc600bf4dc681105cc30c
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=e990234ff6fd0f8d393cc600bf4dc681105cc30c

Author: Kenneth Graunke <kenneth at whitecape.org>
Date:   Wed Jan 29 20:51:28 2014 -0800

i965: Use the new brw_load_register_mem helper for draw indirect.

This makes it work on Broadwell, too.

v2: Drop bogus double write to 3DPRIM_BASE_VERTEX register
    (caught by Chris Forbes).

Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>

---

 src/mesa/drivers/dri/i965/brw_draw.c |   53 ++++++++++++++--------------------
 1 file changed, 22 insertions(+), 31 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c
index 39da953..484c4c1 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -217,42 +217,33 @@ static void brw_emit_prim(struct brw_context *brw,
 
       indirect_flag = GEN7_3DPRIM_INDIRECT_PARAMETER_ENABLE;
 
-      BEGIN_BATCH(15);
-
-      OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM | (3 - 2));
-      OUT_BATCH(GEN7_3DPRIM_VERTEX_COUNT);
-      OUT_RELOC(bo, I915_GEM_DOMAIN_VERTEX, 0,
-            prim->indirect_offset + 0);
-      OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM | (3 - 2));
-      OUT_BATCH(GEN7_3DPRIM_INSTANCE_COUNT);
-      OUT_RELOC(bo, I915_GEM_DOMAIN_VERTEX, 0,
-            prim->indirect_offset + 4);
-      OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM | (3 - 2));
-      OUT_BATCH(GEN7_3DPRIM_START_VERTEX);
-      OUT_RELOC(bo, I915_GEM_DOMAIN_VERTEX, 0,
-            prim->indirect_offset + 8);
-
+      brw_load_register_mem(brw, GEN7_3DPRIM_VERTEX_COUNT, bo,
+                            I915_GEM_DOMAIN_VERTEX, 0,
+                            prim->indirect_offset + 0);
+      brw_load_register_mem(brw, GEN7_3DPRIM_INSTANCE_COUNT, bo,
+                            I915_GEM_DOMAIN_VERTEX, 0,
+                            prim->indirect_offset + 4);
+
+      brw_load_register_mem(brw, GEN7_3DPRIM_START_VERTEX, bo,
+                            I915_GEM_DOMAIN_VERTEX, 0,
+                            prim->indirect_offset + 8);
       if (prim->indexed) {
-         OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM | (3 - 2));
-         OUT_BATCH(GEN7_3DPRIM_BASE_VERTEX);
-         OUT_RELOC(bo, I915_GEM_DOMAIN_VERTEX, 0,
-               prim->indirect_offset + 12);
-         OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM | (3 - 2));
-         OUT_BATCH(GEN7_3DPRIM_START_INSTANCE);
-         OUT_RELOC(bo, I915_GEM_DOMAIN_VERTEX, 0,
-               prim->indirect_offset + 16);
-      }
-      else {
-         OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM | (3 - 2));
-         OUT_BATCH(GEN7_3DPRIM_START_INSTANCE);
-         OUT_RELOC(bo, I915_GEM_DOMAIN_VERTEX, 0,
-               prim->indirect_offset + 12);
+         brw_load_register_mem(brw, GEN7_3DPRIM_BASE_VERTEX, bo,
+                               I915_GEM_DOMAIN_VERTEX, 0,
+                               prim->indirect_offset + 12);
+         brw_load_register_mem(brw, GEN7_3DPRIM_START_INSTANCE, bo,
+                               I915_GEM_DOMAIN_VERTEX, 0,
+                               prim->indirect_offset + 16);
+      } else {
+         brw_load_register_mem(brw, GEN7_3DPRIM_START_INSTANCE, bo,
+                               I915_GEM_DOMAIN_VERTEX, 0,
+                               prim->indirect_offset + 12);
+         BEGIN_BATCH(3);
          OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
          OUT_BATCH(GEN7_3DPRIM_BASE_VERTEX);
          OUT_BATCH(0);
+         ADVANCE_BATCH();
       }
-
-      ADVANCE_BATCH();
    }
    else {
       indirect_flag = 0;