Mesa (broadwell): 97 new commits
Kenneth Graunke
kwg at kemper.freedesktop.org
Thu Jan 23 03:20:30 UTC 2014
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9585ee6daa1b566e19a7a1cd16aa4919e5261189
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Jan 21 00:06:36 2014 -0800
i965: Remove poorly implemented math hstride assertions.
I added this assertion in the last revision of the gen8_fs_generator
patch, and apparently didn't test it enough. Many Piglit tests fail
this test. The destination hstride is 1, while the source hstride and
vstride appear to be 0. This sounds like "scalar source" mode, which is
actually supported.
Cc: Eric Anholt <eric at anholt.net>
Cc: Matt Turner <mattst88 at gmail.com>
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=13da901e1360afa5517700931ca44fed60bee1a1
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Jan 20 23:56:38 2014 -0800
stash - vp fixes?
doesn't seem to actually fix anything.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=52fde4e3bdf5c313ab01e2fd815b50e5859e0613
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Jan 20 23:06:30 2014 -0800
i965: Add missing sample shading bits to Gen8's 3DSTATE_PS_EXTRA.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9403306a8a1d3dafafe96b0f4529433f2b7644af
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Dec 30 22:07:20 2013 -0800
i965: Enable Broadwell support.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=75b6591fd4acd32d493847220c4cd8cdefed92f8
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Nov 1 11:41:34 2013 -0700
i965: Add (disabled) Broadwell PCI IDs.
This puts the PCI IDs in place so it's easy to enable support. However,
it doesn't actually enable support since it's very preliminary still,
and a few crucial pieces (such as BLORP) are still missing.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3bea391696ac78cebb5ff30d01e884ff4e16a51f
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Dec 6 03:07:54 2013 -0800
i965: Disable 3DSTATE_WM_HZ_OP fields.
We'll need to do better than this when we implement multisampling, HiZ,
or fast clears...but for now, this will do.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=74350ad84d5beceba15b2884d0df195bee81ee06
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Nov 4 23:19:55 2013 -0800
i965: Update GS state for Broadwell.
This is quite similar to the Gen7 code. The main changes:
- 48-bit relocations
- Thread count is specified as U/2-1 instead of U-1.
- An extra DWord (DW9) with clip planes, URB entry output length/offsets
- We need to program the "Expected Vertex Count" (VerticesIn)
v2: Set the number of binding table entries so they can be prefetched
(requested by Eric Anholt).
v3: Add a WARN_ONCE for a missing workaround.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Eric Anholt <eric at anholt.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=39d4ae026e15b4725291a4f818668de2546d1e06
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Dec 3 15:20:37 2012 -0800
i965: Update multisampling state for Broadwell.
On previous platforms, 3DSTATE_MULTISAMPLE contained the number of
samples, pixel location, and the positions of each sample within a pixel
for each multisampling mode (4x and 8x). It was also a non-pipelined
command, presumably since changing the sample positions is fairly
drastic.
Broadwell improves upon this by splitting the sample positions out into
a separate non-pipelined state packet, 3DSTATE_SAMPLE_PATTERN. With
that removed, 3DSTATE_MULTISAMPLE becomes a pipelined state packet.
Broadwell also supports 2x and 16x multisampling, in addition to the 4x
and 8x supported by Gen7. This patch, however, does not implement 2x
and 16x.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Chad Versace <chad.versace at linux.intel.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3fb1b6cf6772df9d0673bfe2ed819389e987be0e
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Dec 14 03:58:30 2012 -0800
i965: Update 3DSTATE_{DEPTH,STENCIL,...}_BUFFER and such for Broadwell.
XXX: Can probably just merge this in with the Gen7 code...
not really many changes. OUT_RELOC64 and a few extra DWords (Qpitch)
XXX: lots of these parameters are garbage...
v2: Rebase on Paul's rename of NumLayers -> MaxNumLayers.
v3: Shift QPitch by 2 when storing it in the packet. Bits 14:0 store
bits 16:2 of the actual value. Fixes tests.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8bd0f879de94dd7018d77a07e40b3efa3f62edbe
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Dec 5 19:30:26 2012 -0800
i965: Update BLEND_STATE for Broadwell.
v2: Allow logic ops on all surface types. The UNORM restriction was
lifted with Haswell and I simply hadn't noticed. Also, add missing
BRW_NEW_STATE_BASE_ADDRESS dirty bit. Both caught by Eric Anholt.
v3: Fix swapped per-RT DWord pairs. Eliminates bizarre hacks.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Eric Anholt <eric at anholt.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=83b54d2ec8c69b4f4b02c752f44a0f3ba60a5ef4
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Dec 5 15:34:34 2012 -0800
i965: Update SF_CLIP_VIEWPORT for Broadwell.
It has additional fields to support clipping to the viewport even if
guardband clipping is enabled.
v2: Update for viewport array changes.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Eric Anholt <eric at anholt.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=503dfc94bcb5357cc9e850428a4635c5efa68e84
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Dec 4 16:39:03 2012 -0800
i965: Rework SURFACE_STATE entries for Broadwell.
v2: Add missing SCS setting in gen8_emit_buffer_surface_state (caught by
Eric Anholt).
v3: Use stored QPitch rather than recomputing it.
v4: Shift QPitch by 2 when setting it in the packet; bits 14:0 store
bits 16:2 of the actual value (fixes myriads of cube and array
texturing tests). Also, only enable cube face bits for cubemaps
(matches Chris Forbes' commit on master). Port to use offset64.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f3673ea9f64f07b2adbd520c3f1b8ea4aefd7ffa
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Dec 4 14:45:19 2012 -0800
i965: Update SOL state for Broadwell.
Unlike on Gen7, we can directly set the offset via the state packet.
We also -have- to: the kernel SOL reset code won't work anymore.
v2: Fix copy and paste mistake in buffer stride setup; drop stale
comment (caught by Eric Anholt). Add a perf_debug for missing
MOCS setup.
v3: Rebase on Paul Berry's changes to CurrentVertexProgram.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Eric Anholt <eric at anholt.net> [v2]
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6c45054211d40ca67467369c513fa64cc8242e0d
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Nov 28 21:39:19 2012 -0800
i965: Update the code that disables unused shader stages for Broadwell.
v2: Also disable 3DSTATE_WM_CHROMAKEY for safety.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Eric Anholt <eric at anholt.net> [v1]
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=cce2811e2f96e7c1150a7d21d04c0a0c6ebb013e
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Nov 1 16:29:33 2013 -0700
i965: Update 3DSTATE_CLIP for Broadwell.
Broadwell's winding order, polygon fill, and viewport Z test fields have
moved to DWord 1 of 3DSTATE_RASTER.
v2: Add a perf_debug for a future optimization and improve commit
message (both suggested by Eric Anholt).
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=37b945d03290d659bcc83ee4ea5368ae0f547067
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Dec 3 18:28:29 2012 -0800
i965: Rework vertex uploads for Broadwell.
v2: Emit a dummy 3DSTATE_VF_SGVS packet when not needed.
v3: Add WARN_ONCE and perf_debugs requested by Eric Anholt.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b725242b64cd87be077c6f10eac4f2768f88908f
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Dec 3 13:53:40 2012 -0800
i965: Update STATE_BASE_ADDRESS for Broadwell.
v2: Fix missing "change" bit on instruction state base address
(caught by Haihao Xiang).
v3: Add a perf_debug for missing MOCS setup, requested by Eric.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Eric Anholt <eric at anholt.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2409bf9c94fee50e2005e727d9f7aa576cf10e9a
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Nov 29 21:00:27 2012 -0800
i965: Update 3DSTATE_PS, 3DSTATE_WM, and add 3DSTATE_PS_EXTRA.
v2: Fix setting of GEN8_PSX_ATTRIBUTE_ENABLE after rebases.
v3: Add missing binding table entry counts. Don't worry about alpha
testing or alpha to coverage when setting the "Kill Pixel" bit;
those are specified in 3DSTATE_PS_BLEND (caught by Eric Anholt).
Drop unused _NEW_BUFFERS. Tidy comments.
v4: Rebase on Paul Berry's changes to CurrentFragmentProgram.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Eric Anholt <eric at anholt.net> [v3]
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c38304a66239a57933e7e8e380e3f544d8773809
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Nov 29 01:10:19 2012 -0800
i965: Rework 3DSTATE_VS for Broadwell.
v2: Remove incorrect MOCS shifts; rename urb_entry_write_offset to
urb_entry_output_offset to closer match the documentation.
v3: Only emit a non-zero constant buffer read length when active.
v4: Add missing binding table counts (caught by Eric).
v5: Rebase on Paul Berry's changes to CurrentVertexProgram.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Eric Anholt <eric at anholt.net> [v4]
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=fa25bb488d2b2b53c6cf68bc50755f5e33575906
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Nov 29 18:43:59 2012 -0800
i965: Add the new 3DSTATE_PS_BLEND state packet.
v2: Only set GEN8_PS_BLEND_HAS_WRITEABLE_RT if color buffer writes are
enabled (caught by Eric Anholt).
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Eric Anholt <eric at anholt.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a356e98bb21a6a8d9cfa5496558fe1d0b2e63c7a
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Nov 29 17:52:31 2012 -0800
i965: Replace DEPTH_STENCIL_STATE with Gen8's 3DSTATE_WM_DEPTH_STENCIL.
v2: Use stencil->_WriteEnabled instead of setting
GEN8_WM_DS_STENCIL_BUFFER_WRITE_ENABLE twice (suggested by Eric).
v3: Mask stencil->WriteMask and stencil->ValueMask with 0xff. The field
is only 8-bits, so we'd trip the new SET_FIELD assertion when core
Mesa gave us a value like 0xFFFFFFFF. The Gen7 code uses structure
field widths to implicitly do this truncation. Fixes Piglit tests.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Eric Anholt <eric at anholt.net> [v2]
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=94e1cd9b89bcda0f2a8164e5cf834afd3f5379cd
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Nov 1 14:37:33 2013 -0700
i965: Update SF, SBE, and RASTER state for Broadwell.
The attribute override portion of 3DSTATE_SBE was split out into
3DSTATE_SBE_SWIZ; various bits of 3DSTATE_SF were split out into
3DSTATE_RASTER.
v2: Set Force URB Read Offset bit. Eventually the URB read offset
should be set in 3DSTATE_VS, but that will require some refactoring.
v3: Rebase on viewport array changes.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=70d26198dde70cbf4a474a5e820d39004c3a56d3
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Nov 29 01:50:22 2012 -0800
i965: Bump generation assertions on workaround flushes.
These workaround flushes may not be necessary on Gen8. Investigation is
needed. Tentatively, let's do them out of caution.
v2: [chadv]
- Comment that flush may not be needed.
- Make assertion conditions symmetrical.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Chad Versace <chad.versace at linux.intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=904891bc1950d24f0046cf915c28aa167bab7cc3
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Nov 28 21:16:18 2012 -0800
i965: Duplicate gen7_atoms to gen8_atoms.
It's going to diverge significantly. Starting out with a copy allows
future patches to change atoms one by one.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Eric Anholt <eric at anholt.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3fcab1d9f2a9209dbcac78d3d1ad43b5f0cfe7bd
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Jan 22 16:48:03 2014 -0800
i965: Don't store qpitch / 4 as mt->qpitch for compressed surfaces.
Broadwell requires software to specify QPitch in a bunch of packets,
so we decided to store it in the miptree. However, when I did that
refactoring, I missed a subtlety: the hardware expects QPitch to be
"in units of rows in the uncompressed surface".
This is the value we originally compute. However, for compressed
surfaces, we then divided it by 4 (the block height), to obtain the
physical layout. This is no longer the QPitch Broadwell expects.
So, store the original undivided value in mt->qpitch, but continue to
use the divided value in brw_miptree_layout_texture_array(). For
non-Broadwell platforms, this should have no impact at all.
Helps fix Piglit's "getteximage-targets S3TC CUBE" test on Broadwell.
Cc: Eric Anholt <eric at anholt.net>
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d8c7740ddabeb456243e40dc3cf0e86c7fca09d0
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Jan 15 10:08:38 2014 -0800
i965: Support 32 texture image units on Haswell+.
The Intel closed source OpenGL driver recently began supporting 32
texture image units on Haswell. This makes the open source driver
support 32 as well.
Earlier generations don't have the message header field required to
support more than 16 sampler states, so we continue to advertise 16
there.
On Haswell, this causes us to advertise:
- GL_MAX_TEXTURE_IMAGE_UNITS = 32
- GL_MAX_VERTEX_TEXTURE_IMAGE_UNITS = 32
- GL_MAX_COMBINED_TEXTURE_IMAGE_UNITS = 96
instead of the old values of 16, 16, and 48.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5a51a268044ab191262e6f73f135ca95aa59f5df
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sat Jan 18 14:48:11 2014 -0800
i965/fs: Switch from BRW_MAX_TEX_UNIT to the actual limit.
BRW_MAX_TEX_UNIT is about to grow, but only Gen7+ will be able to
support the new larger value. On older platforms, we don't want to
allocate the extra space - it would just be a waste.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=50ce6f682da57bbbc7b78e99f9aeb9422b05dd6e
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Jan 15 10:08:06 2014 -0800
mesa: Bump MAX_TEXTURE_IMAGE_UNITS to 32.
This allows drivers to optionally support more than 16 texture units.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=15fc919491ea27bd395988a332502bdb23ee44d0
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sat Jan 18 14:32:49 2014 -0800
i965/vec4: Support arbitrarily large sampler state indices on Haswell+.
Like the scalar backend, we add an offset to the "Sampler State Pointer"
field to select a group of 16 samplers, then use the "Sampler Index"
field to select within that group.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d58e03fe4f04c24c70c76e7ad86fd04b9130a711
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sat Jan 18 14:29:19 2014 -0800
i965/vec4: Refactor sampler message setup.
The next patch adds an additional case where the message header is
necessary. So we want to do the g0 copy if inst->header_present is set,
rather than inst->texture_offset.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e0a560291184b7b5ff32afa60a202893ca5a3d77
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sat Jan 18 14:34:07 2014 -0800
i965/vec4: Don't set header_present if texel offsets are all 0.
In theory, a shader might use textureOffset() but set all the texel
offsets to zero. In that case, we don't actually need to set up the
message header - zero is the implicit default.
By moving the texture_offset setup before the header_present setup, we
can easily only set header_present when there are non-zero texel offset
values.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6943ac0bd9d0d07019cffbbcb5189aa8d67b729b
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sat Jan 18 13:29:39 2014 -0800
i965/fs: Support arbitrarily large sampler state indices on Haswell+.
The message descriptor's "Sampler Index" field is only 4 bits (on all
generations of hardware), so it can only represent indices 0 through 15.
Haswell introduced a new field in the message header - "Sampler State
Pointer". Normally, this is copied straight from g0, but we can also
add a byte offset (as long as it's a multiple of 32).
This patch uses a "Sampler State Pointer" offset to select a group of
16 sampler states, and then uses the "Sampler Index" field to select
the state within that group.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d7450e52e67125bfff74510ee4e48bb1ce0751e7
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sat Jan 18 13:28:40 2014 -0800
i965/fs: Plumb sampler index into emit_texture_gen7.
We'll need this in the next patch.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ebfe43d5ad3b00a5ee1b760392a5275bc801c47e
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sat Jan 18 12:48:18 2014 -0800
i965/fs: Refactor sampler message header to duplicate less code.
Previously, the code to copy g0 to the message header existed in two
places - one for the texture offset case, and one for any other case.
By treating texture_offset as a special case of header_present, we can
remove this duplication and shorten the code. Future patches which add
new header fields also won't have to add additional duplication.
This also clarifies a confusing construct. The old code contained:
} else if (inst->header_present) {
if (brw->gen >= 7) {
...explicit copy from g0 to the message header...
} else {
/* Set up an implied move from g0 to the MRF. */
}
}
This looks like it might set up an implied move on Sandybridge, which
doesn't support those. However, Sandybridge only uses a message header
for texture offsets, so it would never hit this code path. The new code
avoids this implicit knowledge by only setting up an implied move on
Gen4-5.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=87e732673598ef3fd08a3432c7975b421b14c8c4
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sat Jan 18 12:49:58 2014 -0800
i965: Use get_element_ud to shorten texture header access.
This is shorter, easier to read, and further from the 80 column limit.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d40532f260c15d56e5fa836147e02c031a999682
Author: Marek Olšák <marek.olsak at amd.com>
Date: Tue Jan 21 19:53:45 2014 +0100
gallium/util: util_format_srgb should not return FORMAT_NONE for sRGB formats
This fixes a serious regression introduced
in 4e549ddb500cf677b6fa16d9ebdfa67cc23da097.
Cc: 9.2 10.0 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Brian Paul <brianp at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d382e90614ff95ddca882b897bc0885d148d2f60
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Jan 17 22:57:39 2014 +0100
gallium: remove PIPE_CAP_SCALED_RESOLVE
If any driver doesn't support this, it can use a blit after resolving
the samples.
Reviewed-by: Brian Paul <brianp at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a8930adbf82560f502e77f818bea5acd6b4ea4ec
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Jan 13 23:42:18 2014 +0100
radeonsi: use hardware scissors correctly
Use the WINDOW and VPORT scissors for the framebuffer and scissor test,
respectively. The other two scissors are disabled (they cover the max fb size).
We actually have 16 VPORT scissors, which will map well to ARB_viewport_array.
Also, we don't need to write SC_WINDOW_OFFSET with this commit, because it's
disabled everywhere.
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=69c29cb147373bfe835789df6fac54821ef62d55
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Jan 13 13:15:19 2014 +0100
radeonsi: handle R600_CONTEXT_PS_PARTIAL_FLUSH in si_emit_cache_flush
For consistency only, This is unused by radeonsi currently.
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5dfb10b2f5e1583eeaef9d7258f1d6a445444e9d
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Jan 13 13:10:06 2014 +0100
r600g,radeonsi: if discarding whole buffer range, discard whole resource instead
Also set the unsynchronized flag if the whole resource was discarded
to avoid doing buffer-busy checks again.
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ee0dc659c849ca9a552edd88d062035cae189068
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Jan 13 13:03:25 2014 +0100
gallium/u_upload_mgr: don't expose u_upload_flush
It's unused and shouldn't be used at all in my opinion.
If some driver doesn't support the unsynchronized flag, u_upload_mgr should
avoid the synchronization by other means, e.g. by using the DONTBLOCK flag.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0c20bff4b626413804486444ad239af620722e2f
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Jan 13 12:59:14 2014 +0100
gallium/hud: just unmap the upload vertex buffer instead of recreating it
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2b033f3aab8267eb6499954fe4a582472f91ef28
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Jan 13 13:51:21 2014 +0100
gallium/vl: use u_upload_mgr to upload vertices for vl_compositor
This is the recommended way for streaming vertices. Always use this if you
need to upload vertices every frame.
Reviewed-by: Christian König <christian.koenig at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=11baad35088dfd4bdabc1710df650dbfb413e7a3
Author: Kristian Høgsberg <krh at bitplanet.net>
Date: Tue Jan 21 12:17:03 2014 -0800
intel: Fix initial MakeCurrent for single-buffer drawables
Commit 05da4a7a5e7d5bd988cb31f94ed8e1f053d9ee39 attempts to eliminate the
call to intel_update_renderbuffer() in the case where we already have a
drawbuffer for the drawable. Unfortunately this only checks the
back left renderbuffer, which breaks in case of single buffer drawables.
This means that the initial viewport will not be set in that case. Instead,
we now check whether the initial viewport has not been set, in which case
we call out to intel_update_renderbuffer().
https://bugs.freedesktop.org/show_bug.cgi?id=73862
Signed-off-by: Kristian Høgsberg <krh at bitplanet.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0da1a2cc369052643ccaea75a1722cc37652d82a
Author: Paul Berry <stereotype441 at gmail.com>
Date: Tue Jan 21 15:41:26 2014 -0800
glsl: Simplify aggregate type inference to prepare for ARB_arrays_of_arrays.
Most of the time it is not necessary to perform type inference to
compile GLSL; the type of every expression can be inferred from the
contents of the expression itself (and previous type declarations).
The exception is aggregate initializers: their type is determined by
the LHS of the variable being assigned to. For example, in the
statement:
mat2 foo = { { 1, 2 }, { 3, 4 } };
the type of { 1, 2 } is only known to be vec2 (as opposed to, say,
ivec2, uvec2, int[2], or a struct) because of the fact that the result
is being assigned to a mat2.
Previous to this patch, we handled this situation by doing some type
inference during parsing: when parsing a declaration like the one
above, we would call _mesa_set_aggregate_type(), which would infer the
type of each aggregate initializer and store it in the corresponding
ast_aggregate_initializer::constructor_type field. Since this
happened at parse time, we couldn't do the type inference using
glsl_type objects; we had to use ast_type_specifiers, which are much
more awkward to work with. Things are about to get more complicated
when we add support for ARB_arrays_of_arrays.
This patch simplifies things by postponing the call to
_mesa_set_aggregate_type() until ast-to-hir time, when we have access
to glsl_type objects. As a side benefit, we only need to have one
call to _mesa_set_aggregate_type() now, instead of six.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6ec210989fa10847091f06fcfcab77dd07618dff
Author: Jan Vesely <jan.vesely at rutgers.edu>
Date: Thu Jan 16 20:22:14 2014 -0500
clover: Don't crash on NULL global buffer objects.
Specs say "If the argument is a buffer object, the arg_value
pointer can be NULL or point to a NULL value in which case a NULL
value will be used as the value for the argument declared as a
pointer to __global or __constant memory in the kernel."
So don't crash when somebody does that.
v2: Insert NULL into input buffer instead of buffer handle pair
Fix constant_argument too
Drop r600 driver changes
v3: Fix inserting NULL pointer
Signed-off-by: Jan Vesely <jan.vesely at rutgers.edu>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6caf34b97e5d22f5910695e30941bea3d0bf2e46
Author: Vinson Lee <vlee at freedesktop.org>
Date: Tue Jan 21 22:46:39 2014 -0800
meta: Move loop variable declaration outside loop.
Fixes MSVC build error introduced with commit
69b258cb4636315b4c1aaaceeedd1eed8af98ba8.
meta.c(618) : error C2143: syntax error : missing ';' before 'type'
meta.c(618) : error C2143: syntax error : missing ')' before 'type'
meta.c(618) : error C2065: 'i' : undeclared identifier
meta.c(618) : warning C4552: '<' : operator has no effect; expected operator with side-effect
meta.c(618) : error C2059: syntax error : ')'
meta.c(618) : error C2143: syntax error : missing ';' before '{'
meta.c(619) : error C2065: 'i' : undeclared identifier
meta.c(620) : error C2065: 'i' : undeclared identifier
Signed-off-by: Vinson Lee <vlee at freedesktop.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8b16b0255b3163acf2061e3c612efe6893333171
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date: Tue Jan 21 11:33:58 2014 +0200
i965/blorp: use BRW_COMPRESSION_2NDHALF for second half LPR
No known bugs fixed but this is now in line with fs-generator.
No regresssions on IVB.
Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Reviewed-by: Paul Berry <stereotype441 at gmail.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=89347dd61b7271bcca450332454253128eb10d4e
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date: Tue Jan 21 10:31:10 2014 +0200
i965/blorp: patch jump counters also for endif
No known bugs fixed but this is now in line with fs-generator.
No regresssions on IVB.
Eric further explained that:
"The endif jump, since it's forward, is just an optimization to
have set right -- otherwise, the GPU will just step forward
instruction by instruction until it hits something else that
updates the per-channel PC."
Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Reviewed-by: Paul Berry <stereotype441 at gmail.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Eric Anholt <eric at anholt.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1032c33cb93f1e8839be0f743b81492c2ca87e39
Author: Paul Berry <stereotype441 at gmail.com>
Date: Thu Jan 9 11:34:33 2014 -0800
mesa: Change redundant code into loops in texstate.c.
This is possible now that ctx->Shader.CurrentProgram is an array.
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
Reviewed-by: Brian Paul <brianp at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6ac2e1e199ff02ad720495a64c0755fcae981671
Author: Paul Berry <stereotype441 at gmail.com>
Date: Thu Jan 9 11:33:15 2014 -0800
mesa: Change redundant code into loops in shaderapi.c.
This is possible now that ctx->Shader.CurrentProgram is an array.
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
Reviewed-by: Brian Paul <brianp at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5808c44bab52fdb58ad705e08e334c6f1acdd2ce
Author: Paul Berry <stereotype441 at gmail.com>
Date: Thu Jan 9 11:32:00 2014 -0800
mesa: Remove ad-hoc arrays of gl_shader_program.
Now that we have a ctx->Shader.CurrentProgram array, we can just use
it directly.
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
Reviewed-by: Brian Paul <brianp at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=69b258cb4636315b4c1aaaceeedd1eed8af98ba8
Author: Paul Berry <stereotype441 at gmail.com>
Date: Thu Jan 9 11:29:17 2014 -0800
meta: Replace save_state::{Vertex,Geometry,Fragment}Shader with an array.
Since ctx->Shader.Current{Vertex,Geometry,Fragment}Program is an
array, this allows some meta code to be rolled up into loops.
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
Reviewed-by: Brian Paul <brianp at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b4b70674eae940257b511912053edd19e4f19274
Author: Paul Berry <stereotype441 at gmail.com>
Date: Thu Jan 9 11:28:20 2014 -0800
i965: Fix comments to refer to the new ctx->Shader.CurrentProgram array.
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
Reviewed-by: Brian Paul <brianp at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1aef45578ced422df622a251fcce83bbe01d617e
Author: Paul Berry <stereotype441 at gmail.com>
Date: Thu Jan 9 11:27:38 2014 -0800
mesa: Fold long lines introduced by the previous patch.
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
Reviewed-by: Brian Paul <brianp at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3b22146dc714b6090f7423abbc4df53d7d1fdaa9
Author: Paul Berry <stereotype441 at gmail.com>
Date: Thu Jan 9 11:16:27 2014 -0800
mesa: Replace ctx->Shader.Current{Vertex,Fragment,Geometry}Program with an array.
These are replaced with
ctx->Shader.CurrentProgram[MESA_SHADER_{VERTEX,FRAGMENT,GEOMETRY}].
In patches to follow, this will allow us to replace a lot of ad-hoc
logic with a variable index into the array.
With the exception of the changes to mtypes.h, this patch was
generated entirely by the command:
find src -type f '(' -iname '*.c' -o -iname '*.cpp' ')' \
-print0 | xargs -0 sed -i \
-e 's/\.CurrentVertexProgram/.CurrentProgram[MESA_SHADER_VERTEX]/g' \
-e 's/\.CurrentGeometryProgram/.CurrentProgram[MESA_SHADER_GEOMETRY]/g' \
-e 's/\.CurrentFragmentProgram/.CurrentProgram[MESA_SHADER_FRAGMENT]/g'
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
Reviewed-by: Brian Paul <brianp at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=cd18ba1c7aba66f2dd7cdbe2cf3b4a803c241d10
Author: Paul Berry <stereotype441 at gmail.com>
Date: Tue Jan 7 08:56:57 2014 -0800
glsl/linker: Refactor in preparation for adding more shader stages.
Rather than maintain separately named arrays and counts for vertex,
geometry, and fragment shaders, just maintain these as arrays indexed
by the gl_shader_type enum.
v2: When there is neither a vertex nor a geometry shader, set
prog->LastClipDistanceArraySize = 0, and clarify that the values is
not used.
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
Reviewed-by: Brian Paul <brianp at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4a91675b262c8150c1542991e1018e924c72f337
Author: Paul Berry <stereotype441 at gmail.com>
Date: Tue Jan 7 15:19:07 2014 -0800
mesa: use _mesa_validate_shader_target() more frequently.
This patch replaces code in _mesa_new_shader() and delete_shader_cb()
that checks the type of a shader with calls to
_mesa_validate_shader_target(). This has two advantages: it allows
for a more thorough check (since _mesa_validate_shader_target()
doesn't permit shader targets that aren't supported by the back-end),
and it reduces the amount of code that will need to be modified when
adding new shader stages.
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
Reviewed-by: Brian Paul <brianp at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=020919b2ae76192f0f35c0901be0e1069a87b7f2
Author: Paul Berry <stereotype441 at gmail.com>
Date: Thu Jan 9 15:30:10 2014 -0800
main: Allow ctx == NULL in _mesa_validate_shader_target().
This will allow this function to be used in circumstances where there
is no context available, such as when building built-in GLSL
functions.
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
Reviewed-by: Brian Paul <brianp at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6ab2a6148a539a9e308ad4e017e5ed6b9658aa4f
Author: Paul Berry <stereotype441 at gmail.com>
Date: Tue Jan 7 15:13:52 2014 -0800
mesa: Make validate_shader_target() non-static.
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
Reviewed-by: Brian Paul <brianp at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=46d210d38fc472d5454cef864c4299c52bb46c86
Author: Paul Berry <stereotype441 at gmail.com>
Date: Thu Jan 9 13:42:05 2014 -0800
mesa: Replace _mesa_program_index_to_target with _mesa_shader_stage_to_program.
In my recent zeal to refactor Mesa's handling of the gl_shader_stage
enum, I accidentally wound up with two functions that do the same
thing: _mesa_program_index_to_target(), and
_mesa_shader_stage_to_program().
This patch keeps _mesa_shader_stage_to_program(), since its name is
more consistent with other related functions. However, it changes the
signature so that it accepts an unsigned integer instead of a
gl_shader_stage--this avoids awkward casts when the function is called
from C++ code.
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
Reviewed-by: Brian Paul <brianp at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2212a97fe36f0d20c4c8dc1db1a3c7da08126f95
Author: Dave Airlie <airlied at redhat.com>
Date: Tue Jan 21 14:54:05 2014 +1000
llvmpipe: dump geometry shaders when using LP_DEBUG=tgsi
for consistency with vs and fs dumpers.
Reviewed-by: Brian Paul <brianp at vmware.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=178c1bf1adef9e3871b1ec35da839fc04fe481cf
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Wed Dec 18 14:43:19 2013 -0800
mesa: Generate GL_INVALID_OPERATION for unsupported DSA TexStorage functions
We have to make the functions available to work around a GLEW bug (see
comments already in the code), but if an application calls one of these
functions we should still generate GL_INVALID_OPERATION.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=17594dccfd625556f866dcac322fc65ad81e37f3
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Wed Dec 18 14:39:26 2013 -0800
mesa: Silence many unused parameter warnings
main/texstorage.c: In function '_mesa_alloc_texture_storage':
main/texstorage.c:240:53: warning: unused parameter 'width' [-Wunused-parameter]
main/texstorage.c:241:37: warning: unused parameter 'height' [-Wunused-parameter]
main/texstorage.c:241:53: warning: unused parameter 'depth' [-Wunused-parameter]
main/texstorage.c: In function '_mesa_TextureStorage1DEXT':
main/texstorage.c:464:34: warning: unused parameter 'texture' [-Wunused-parameter]
main/texstorage.c:464:50: warning: unused parameter 'target' [-Wunused-parameter]
main/texstorage.c:464:66: warning: unused parameter 'levels' [-Wunused-parameter]
main/texstorage.c:465:34: warning: unused parameter 'internalformat' [-Wunused-parameter]
main/texstorage.c:466:35: warning: unused parameter 'width' [-Wunused-parameter]
main/texstorage.c: In function '_mesa_TextureStorage2DEXT':
main/texstorage.c:473:34: warning: unused parameter 'texture' [-Wunused-parameter]
main/texstorage.c:473:50: warning: unused parameter 'target' [-Wunused-parameter]
main/texstorage.c:473:66: warning: unused parameter 'levels' [-Wunused-parameter]
main/texstorage.c:474:34: warning: unused parameter 'internalformat' [-Wunused-parameter]
main/texstorage.c:475:35: warning: unused parameter 'width' [-Wunused-parameter]
main/texstorage.c:475:50: warning: unused parameter 'height' [-Wunused-parameter]
main/texstorage.c: In function '_mesa_TextureStorage3DEXT':
main/texstorage.c:483:34: warning: unused parameter 'texture' [-Wunused-parameter]
main/texstorage.c:483:50: warning: unused parameter 'target' [-Wunused-parameter]
main/texstorage.c:483:66: warning: unused parameter 'levels' [-Wunused-parameter]
main/texstorage.c:484:34: warning: unused parameter 'internalformat' [-Wunused-parameter]
main/texstorage.c:485:35: warning: unused parameter 'width' [-Wunused-parameter]
main/texstorage.c:485:50: warning: unused parameter 'height' [-Wunused-parameter]
main/texstorage.c:485:66: warning: unused parameter 'depth' [-Wunused-parameter]
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f5cfb4ae21df8eebfc6b86c0ce858b1c0a9160dd
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Wed Jan 15 10:23:02 2014 -0800
i965: Ignore 'centroid' interpolation qualifier in case of persample shading
This patch handles the use of 'centroid' qualifier with 'in' variables
in a fragment shader when persample shading is enabled. Per sample
shading for the whole fragment shader can be enabled by:
glEnable(GL_SAMPLE_SHADING) or using {gl_SamplePosition, gl_SampleID}
builtin variables in fragment shader. Explaining it below in more
detail.
/* Enable sample shading using OpenGL API */
glEnable(GL_SAMPLE_SHADING);
glMinSampleShading(1.0);
Example fragment shader:
in vec4 a;
centroid in vec4 b;
main()
{
...
}
Variable 'a' will be interpolated at sample location. But, what
interpolation should we use for variable 'b' ?
ARB_sample_shading recommends interpolation at sample position for
all the variables. GLSL 400 (and earlier) spec says that:
"When an interpolation qualifier is used, it overrides settings
established through the OpenGL API."
But, this text got deleted in later versions of GLSL.
NVIDIA's and AMD's proprietary linux drivers (at OpenGL 4.3)
interpolates at sample position. This convinces me to use
the similar approach on intel hardware.
Cc: mesa-stable at lists.freedesktop.org
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a92e5f7cf63d496ad7830b5cea4bbab287c25b8e
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Mon Jan 6 13:59:18 2014 -0800
i965: Use sample barycentric coordinates with per sample shading
Current implementation of arb_sample_shading doesn't set 'Barycentric
Interpolation Mode' correctly. We use pixel barycentric coordinates
for per sample shading. Instead we should select perspective sample
or non-perspective sample barycentric coordinates.
It also enables using sample barycentric coordinates in case of a
fragment shader variable declared with 'sample' qualifier.
e.g. sample in vec4 pos;
A piglit test to verify the implementation has been posted on piglit
mailing list for review.
V2: Do not interpolate all the 'in' variables at sample position
if fragment shader uses 'sample' qualifier with one of them.
For example we have a fragment shader:
#version 330
#extension ARB_gpu_shader5: require
sample in vec4 a;
in vec4 b;
main()
{
...
}
Only 'a' should be sampled at sample location, not 'b'.
Cc: mesa-stable at lists.freedesktop.org
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3313cc269bd428ca96a132d86da5fddc0f27386a
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Mon Jan 13 12:26:55 2014 -0800
i965: Add an option to ignore sample qualifier
This will be useful in my next patch which depends on a functionality
of _mesa_get_min_invocations_per_fragment() to ignore the sample
qualifier (prog->IsSample) based on a flag passed to it.
Cc: mesa-stable at lists.freedesktop.org
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=78d65476b69402dc1d82b35e7ba3047ef44d783a
Author: Matt Turner <mattst88 at gmail.com>
Date: Sat Jan 11 20:37:51 2014 -0800
mesa/x86: Remove dead read_rgba_span_x86.h.
Dead since 304f7a13.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=bf0773aeca86669371d99eadb928c6dc92d5840a
Author: Matt Turner <mattst88 at gmail.com>
Date: Thu Jan 9 20:57:36 2014 -0800
i965/fs: Optimize LRP with x == y into a MOV.
total instructions in shared programs: 1487331 -> 1485988 (-0.09%)
instructions in affected programs: 45638 -> 44295 (-2.94%)
GAINED: 7
LOST: 0
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8d37e9915a3b21b496269a39f677a80a6e02cb2c
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Mon Nov 4 10:23:24 2013 -0800
glsl: Optimize open-coded lrp into lrp.
total instructions in shared programs: 1498191 -> 1487051 (-0.74%)
instructions in affected programs: 669388 -> 658248 (-1.66%)
GAINED: 1
LOST: 0
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=13100ac142e935c422018d5152b27ce3564def08
Author: Matt Turner <mattst88 at gmail.com>
Date: Fri Jan 3 14:52:55 2014 -0800
i965: Enable AOS optimizations for the geometry shader.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4bd6e0d7c69b304be88996a6c2b96ce7d996e627
Author: Matt Turner <mattst88 at gmail.com>
Date: Sat Dec 21 11:28:05 2013 -0800
glsl: Vectorize multiple scalar assignments
Reduces vertex shader instruction counts in DOTA2 by 6.42%, L4D2 by
4.61%, and CS:GO by 5.71%.
total instructions in shared programs: 1500153 -> 1498191 (-0.13%)
instructions in affected programs: 59919 -> 57957 (-3.27%)
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5e82d8a9da9eeab33e2819c2d90f1419e42cb33d
Author: Matt Turner <mattst88 at gmail.com>
Date: Wed Jan 1 16:52:32 2014 -0800
glsl: Add parameter to .equals() to ignore an IR type.
Only implemented for ir_swizzles currently, but perhaps will be useful
for other IR types in the future.
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ebf91993c18bdf90c4699b42e58cb84d0b160f25
Author: Matt Turner <mattst88 at gmail.com>
Date: Fri Jan 3 14:48:53 2014 -0800
mesa: rename PreferDP4 to OptimizeForAOS.
This flag was really just a proxy for determining whether the backend
was vector (AOS) or scalar (SOA). It will be used to apply a future
optimization only for vector backends.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=413622fbefb63c54d331ce5d708479ab847e6709
Author: Matt Turner <mattst88 at gmail.com>
Date: Sat Dec 14 18:37:16 2013 -0800
i965/fs: Print the maximum register pressure.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=391eaa59bd2b71078a28ff34dd3d4eed470653ee
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sun Aug 4 23:34:01 2013 -0700
i965/fs: Show register pressure in dump_instructions() output.
Dumping the number of live registers at each IP allows us to see
register pressure and identify any local maxima. This should
aid in debugging passes designed to reduce register pressure, as
well as optimizations that suddenly trigger spilling.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3b74f4b2333704bc7dbe5714e1f2aa4d201669ee
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sun Aug 4 23:27:14 2013 -0700
i965: Compute the number of live registers at each IP.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0ea600ef1ada70bc2280909d86abe29dfd3e8f73
Author: Matt Turner <mattst88 at gmail.com>
Date: Sun Dec 15 20:07:05 2013 -0800
i965/fs: Call opt_peephole_sel later in the optimization loop.
Calling it after value numbering (added in the next commit) prevents
some instruction count regressions.
total instructions in shared programs: 1524387 -> 1523905 (-0.03%)
instructions in affected programs: 13112 -> 12630 (-3.68%)
GAINED: 0
LOST: 3
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ede6c341f686def647bf8ee4912e759b3d9933a6
Author: Matt Turner <mattst88 at gmail.com>
Date: Sun Dec 15 15:39:29 2013 -0800
i965/fs: Calculate interference better in register_coalesce.
Previously we simply considered two registers whose live ranges
overlapped to interfere. Cases such as
set A ------
... |
mov B, A -- |
... | B | A
use B -- |
... |
use A ------
would be considered to interfere, even though B is an unmodified copy of
A whose live range fit wholly inside that of A.
If no writes to A or B occur between the mov B, A and the use of B then
we can safely coalesce them.
Instead of removing MOV instructions, we make them NOPs and remove them
at once after the main pass is finished in order to avoid recomputing
live intervals (which are needed to perform the previous step).
total instructions in shared programs: 1543768 -> 1513077 (-1.99%)
instructions in affected programs: 951563 -> 920872 (-3.23%)
GAINED: 46
LOST: 22
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4a7d0c550e28ae3d434da81c9029272d22fa315e
Author: Matt Turner <mattst88 at gmail.com>
Date: Tue Dec 10 16:04:27 2013 -0800
i965/fs: Support coalescing registers of size > 1.
total instructions in shared programs: 1550048 -> 1549880 (-0.01%)
instructions in affected programs: 1896 -> 1728 (-8.86%)
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=78fa6172e11159a32fc5bb222965fd53eb39976e
Author: Matt Turner <mattst88 at gmail.com>
Date: Sat Dec 7 16:22:08 2013 -0800
i965/fs: Assert that var < num_vars.
Helped to track down a problem in a version of the next commit.
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9bb4d71fd2ff8ed24cb4d1485df1f1ff667bcb3c
Author: Matt Turner <mattst88 at gmail.com>
Date: Tue Dec 10 16:05:19 2013 -0800
i965/fs: Add a comment explaining how register coalescing works.
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2dfb0671395c383caf360a5690756f77afef6663
Author: Matt Turner <mattst88 at gmail.com>
Date: Tue Dec 10 16:22:56 2013 -0800
i965/fs: Add and use MAX_SAMPLER_MESSAGE_SIZE definition.
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=81d52419cfaf143d9f157a2eff148a940a05ca69
Author: Matt Turner <mattst88 at gmail.com>
Date: Tue Dec 10 16:21:16 2013 -0800
mesa: Add STRINGIFY macro.
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=80b949f16b3461c65273bb5d0e263dfffaab400e
Author: Matt Turner <mattst88 at gmail.com>
Date: Sat Dec 7 12:59:59 2013 -0800
i965/fs: Fix the example about overwriting uniforms in SIMD16.
mov takes only a single source argument. Example instruction
inexplicably changed from add to mov in commit f10f5e49.
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=71bc11a37508542662132b16a53acd5f541cd2b4
Author: Matt Turner <mattst88 at gmail.com>
Date: Wed Dec 4 15:01:16 2013 -0800
i965: Print reg_offset for vgrf of size > 1 in dump_instruction().
Previously we wouldn't print the +0 for the first part of a VGRF of size
greater than 1.
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=955c93dc089f85fe52f4f34971ffcca43eb87310
Author: Grigori Goronzy <greg at chown.ath.cx>
Date: Wed Nov 27 00:15:06 2013 +0100
glsl: Match unnamed record types across stages.
Unnamed record types are assigned to separate types per stage, e.g. if
uniform struct { ... } a;
is defined in both vertex and fragment shader, two separate types will
result with different names. When linking the shader, this results in a
type conflict. However, there is no reason why this should not be
allowed according to GLSL specifications. Compare and match record types
when linking shader stages to avoid this conflict.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=41c9bf884ff266e9c2286002446ed2297838086f
Author: Grigori Goronzy <greg at chown.ath.cx>
Date: Wed Nov 27 00:15:05 2013 +0100
glsl: Extract function for record comparisons.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6d8cf5181a09913eb856cfd2914d09a1644c26be
Author: Brian Paul <brianp at vmware.com>
Date: Fri Jan 17 08:18:32 2014 -0800
docs: remove some ancient README.* files
None of this info is relevant anymore.
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b9f68d927ea5e114b6019c807ce65674d9fa1d1d
Author: Brian Paul <brianp at vmware.com>
Date: Thu Jan 16 18:32:47 2014 -0800
svga: implement TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
Fixes several colorbuffer tests, including piglit "fbo-drawbuffers-none"
for "gl_FragColor" and "glDrawPixels" cases.
v2: rework patch to only avoid creating extra shader variants when
TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS is not specified. Per Jose.
Use a write_color0_to_n_cbufs key field to replicate color0 to N
color buffers only when N > 0 and WRITES_ALL_CBUFS is set.
Reviewed-by: José Fonseca <jfonseca at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=384fd64ab1533df8256600733a1fc8413af3514a
Author: Brian Paul <brianp at vmware.com>
Date: Thu Jan 16 18:05:00 2014 -0800
svga: rename color output variables
Just to be bit more readable.
Reviewed-by: José Fonseca <jfonseca at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f6bc7d658677cd7750575147a6c50d2b681b6e35
Author: Brian Paul <brianp at vmware.com>
Date: Thu Jan 16 18:01:57 2014 -0800
svga: fix clearing for null color buffers
Fixes piglit "fbo-drawbuffers-none glClear" test.
Reviewed-by: José Fonseca <jfonseca at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ff59b3d9ee3204a16d991087f71808e41054cc85
Author: Brian Paul <brianp at vmware.com>
Date: Tue Jan 21 08:18:13 2014 -0800
mesa: add missing TYPE_DOUBLEN_2 cases in get.c
The new TYPE_DOUBLEN_2 type was added in 0e60d850 but the code to
return values of that type wasn't completed.
Fixes conform's default state test. glGetFloatv(GL_DEPTH_RANGE)
wasn't returning anything.
v2: remove stray 'break' statements.
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=51000c2ff8a6b59b6dab51cbd63ef87ac6f2a317
Author: Paul Berry <stereotype441 at gmail.com>
Date: Sat Mar 23 07:22:08 2013 -0700
i965: Modify some error messages to refer to "vec4" instead of "vs".
These messages are in code that is shared between the VS and GS
back-ends, so use the terminology "vec4" to avoid confusion.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a4d68e9ee94cf4855a3240c3516279b4e7740268
Author: Paul Berry <stereotype441 at gmail.com>
Date: Fri Jan 17 14:42:48 2014 -0800
i965: Add GS support to INTEL_DEBUG=shader_time.
Previously, time spent in geometry shaders would be counted as part of
the vertex shader time.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e23e4f67bed51a8dfd182eae6c7e8e23a7d2cb0e
Author: Roland Scheidegger <sroland at vmware.com>
Date: Tue Jan 21 17:47:08 2014 +0100
draw: fix points with negative w coords for d3d style point clipping
Even with depth clipping disabled, vertices which have negative w coords
must be discarded. And since we don't have a proper guardband implementation
yet (relying on driver to handle all values except infs/nans in rasterization
for such points) we need to kill them off manually (as they can end up with
coordinates inside viewport otherwise).
v2: use 0.0f instead of 0 (spotted by Brian).
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ad04e396faaddce926ee1146f0da12b30aee7b87
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Nov 5 16:55:06 2013 -0800
i965: Reserve space for "Vertex Count" in GS outputs.
v2: Also increment ir->offset in the GS visitor, rather than at the
final assembly generation stage (requested by Paul).
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Paul Berry <stereotype441 at gmail.com>
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