Mesa (master): i965/vec4: Combine generate_math[12]_gen6 methods.
Kenneth Graunke
kwg at kemper.freedesktop.org
Tue Jun 10 23:39:05 UTC 2014
Module: Mesa
Branch: master
Commit: f3ddd71f2878e42d2c9e927bd5f695a62b357c58
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f3ddd71f2878e42d2c9e927bd5f695a62b357c58
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sat Jun 7 02:32:40 2014 -0700
i965/vec4: Combine generate_math[12]_gen6 methods.
These are trivial to combine: we should just avoid checking the second
operand if it's brw_null_reg.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
---
src/mesa/drivers/dri/i965/brw_vec4.h | 11 +++-----
src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 29 ++++++----------------
2 files changed, 12 insertions(+), 28 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h b/src/mesa/drivers/dri/i965/brw_vec4.h
index d8fa20b..614ff0b 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -654,17 +654,14 @@ private:
void generate_math1_gen4(vec4_instruction *inst,
struct brw_reg dst,
struct brw_reg src);
- void generate_math1_gen6(vec4_instruction *inst,
- struct brw_reg dst,
- struct brw_reg src);
void generate_math2_gen4(vec4_instruction *inst,
struct brw_reg dst,
struct brw_reg src0,
struct brw_reg src1);
- void generate_math2_gen6(vec4_instruction *inst,
- struct brw_reg dst,
- struct brw_reg src0,
- struct brw_reg src1);
+ void generate_math_gen6(vec4_instruction *inst,
+ struct brw_reg dst,
+ struct brw_reg src0,
+ struct brw_reg src1);
void generate_tex(vec4_instruction *inst,
struct brw_reg dst,
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
index 86dfbd5..119bcae 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
@@ -177,30 +177,17 @@ check_gen6_math_src_arg(struct brw_reg src)
}
void
-vec4_generator::generate_math1_gen6(vec4_instruction *inst,
- struct brw_reg dst,
- struct brw_reg src)
-{
- /* Can't do writemask because math can't be align16. */
- assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
- check_gen6_math_src_arg(src);
-
- brw_set_default_access_mode(p, BRW_ALIGN_1);
- gen6_math(p, dst, brw_math_function(inst->opcode), src, brw_null_reg());
- brw_set_default_access_mode(p, BRW_ALIGN_16);
-}
-
-void
-vec4_generator::generate_math2_gen6(vec4_instruction *inst,
- struct brw_reg dst,
- struct brw_reg src0,
- struct brw_reg src1)
+vec4_generator::generate_math_gen6(vec4_instruction *inst,
+ struct brw_reg dst,
+ struct brw_reg src0,
+ struct brw_reg src1)
{
/* Can't do writemask because math can't be align16. */
assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
/* Source swizzles are ignored. */
check_gen6_math_src_arg(src0);
- check_gen6_math_src_arg(src1);
+ if (src1.file == BRW_GENERAL_REGISTER_FILE)
+ check_gen6_math_src_arg(src1);
brw_set_default_access_mode(p, BRW_ALIGN_1);
gen6_math(p, dst, brw_math_function(inst->opcode), src0, src1);
@@ -1129,7 +1116,7 @@ vec4_generator::generate_vec4_instruction(vec4_instruction *instruction,
gen6_math(p, dst, brw_math_function(inst->opcode), src[0],
brw_null_reg());
} else if (brw->gen == 6) {
- generate_math1_gen6(inst, dst, src[0]);
+ generate_math_gen6(inst, dst, src[0], brw_null_reg());
} else {
generate_math1_gen4(inst, dst, src[0]);
}
@@ -1141,7 +1128,7 @@ vec4_generator::generate_vec4_instruction(vec4_instruction *instruction,
if (brw->gen >= 7) {
gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
} else if (brw->gen == 6) {
- generate_math2_gen6(inst, dst, src[0], src[1]);
+ generate_math_gen6(inst, dst, src[0], src[1]);
} else {
generate_math2_gen4(inst, dst, src[0], src[1]);
}
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