Mesa (master): i965: Use the spill destination for the message header on GEN >= 7
Jason Ekstrand
jekstrand at kemper.freedesktop.org
Mon Oct 27 20:36:29 UTC 2014
Module: Mesa
Branch: master
Commit: 4242eb14c1dab83b29e63a4833400ff600cc9f96
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4242eb14c1dab83b29e63a4833400ff600cc9f96
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Fri Oct 24 12:22:04 2014 -0700
i965: Use the spill destination for the message header on GEN >= 7
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
---
src/mesa/drivers/dri/i965/brw_eu_emit.c | 19 +++++++++++++------
1 file changed, 13 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index 92f19e2..bb6334b 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -2099,7 +2099,18 @@ brw_oword_block_read_scratch(struct brw_compile *p,
if (brw->gen >= 6)
offset /= 16;
- mrf = retype(mrf, BRW_REGISTER_TYPE_UD);
+ if (p->brw->gen >= 7) {
+ /* On gen 7 and above, we no longer have message registers and we can
+ * send from any register we want. By using the destination register
+ * for the message, we guarantee that the implied message write won't
+ * accidentally overwrite anything. This has been a problem because
+ * the MRF registers and source for the final FB write are both fixed
+ * and may overlap.
+ */
+ mrf = retype(dest, BRW_REGISTER_TYPE_UD);
+ } else {
+ mrf = retype(mrf, BRW_REGISTER_TYPE_UD);
+ }
dest = retype(dest, BRW_REGISTER_TYPE_UW);
if (num_regs == 1) {
@@ -2118,11 +2129,7 @@ brw_oword_block_read_scratch(struct brw_compile *p,
brw_MOV(p, mrf, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
/* set message header global offset field (reg 0, element 2) */
- brw_MOV(p,
- retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE,
- mrf.nr,
- 2), BRW_REGISTER_TYPE_UD),
- brw_imm_ud(offset));
+ brw_MOV(p, get_element_ud(mrf, 2), brw_imm_ud(offset));
brw_pop_insn_state(p);
}
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