Mesa (master): 36 new commits
Iago Toral Quiroga
itoral at kemper.freedesktop.org
Fri Sep 19 13:06:47 UTC 2014
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=74d7ff2efda8e33e097ed6e3f9853fc1c8d45618
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Wed Jul 9 13:19:34 2014 +0200
i965/gen6: enable GLSL 1.50, OpenGL 3.2 and GL_AMD_vertex_shader_layered
Geometry shaders was the only thing we needed to enable GLSL 1.50 and
OpenGL 3.2 in gen6.
v2: Layered clears do not work properly in gen6 with OpenGL 3.2. Kenneth
and Jordan realized that for this to work we also need
GL_AMD_vertex_shader_layered (which requires OpenGL 3.2, so it could not be
enabled before this patch), so we agreed to enable this together with
OpenGL 3.2 in this patch.
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d2c2ca9ee81dd1bd9139e8820f5d696ba9f2e430
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Tue Jul 1 12:43:59 2014 +0200
i965/gen6/gs: Use a specific implementation of geometry shaders for gen6.
In gen6 we will use the geometry shader implementation from gen6_gs_visitor.cpp
and keep the implementation in brw_vec4_gs_visitor.cpp for gen7+. Notice that
gen6_gs_visitor inherits from brw_vec4_gs_visitor so it is not a completely
seprate implementation of geometry shaders.
Also, gen6 does not support multiple dispatch modes, its default operation mode
is equivalent to gen7's SINGLE mode, so select that in gen6 for consistency.
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3a4aee34a24a7af7cc2f2a75ca4f5eae533b6f88
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Thu Aug 7 11:16:57 2014 +0200
i965/gen6/gs: upload ubo and pull constants surfaces.
Uniforms declared as uniform blocks are stored in ubo surfaces and need to
be pulled from the geometry shader program so make sure we upload them first
and do the same for pull constants.
This fixes all piglit tests that use uniform blocks:
bin/shader_runner tests/spec/glsl-1.50/uniform_buffer/gs-*
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6947a8a593ce1252ef380d653f29f8e225ef8b83
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Fri Jul 18 13:04:36 2014 +0200
i965/gen6/gs: Enable transform feedback support in geometry shaders
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c66165ab2b15047792808433b788632a4b9df287
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Fri Aug 1 10:35:20 2014 +0200
i965/gen6/gs: Fix binding table clash between TF surfaces and textures.
For gen6 geometry shaders we use the first BRW_MAX_SOL_BINDINGS entries of the
binding table for transform feedback surfaces. However, vec4_visitor will
setup the binding table so that textures use the same space in the binding
table. This is done when calling assign_common_binding_table_offsets(0) as
part if its run() method.
To fix this clash we add a virtual method to the vec4_visitor hierarchy to
assign the binding table offsets, so that we can change this behavior
specifically for gen6 geometry shaders by mapping textures right after the
first BRW_MAX_SOL_BINDINGS entries.
Also, when there is no user-provided geometry shader, we only need to upload
the binding table if we have transform feedback, however, in the case of a
user-provided geometry shader, we can't only look into transform feedback
to make that decision.
This fixes multiple piglit tests for textureSize() and texelFetch() when these
functions are called from a geometry shader in gen6, like these:
bin/textureSize gs sampler2D -fbo -auto
bin/texelFetch gs usampler2D -fbo -auto
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2614cde9981ee3609b8e22d84596603a1bd42212
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Wed Aug 13 12:14:22 2014 +0200
i965/gen6/gs: Avoid buffering transform feedback varyings twice.
Currently we buffer transform feedack varyings separately. This patch makes
it so that we reuse the values we have already buffered for all the output
varyings of the geometry shader instead.
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=21204434845398de86fb707c78dd5bdd1fb5826f
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Thu Jul 31 13:27:30 2014 +0200
i965/gen6/gs: Buffer PSIZ/flags vertex data in gen6_gs_visitor
Since geometry shaders can alter the value of varyings packed in the first
output VUE slot (PSIZ), we need to buffer it together with all the other
vertex data so we can emit the right value for each vertex when we do the
URB writes.
This fixes the following piglit test in gen6:
tests/spec/glsl-1.50/execution/redeclare-pervertex-out-subset-gs.shader_test
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=28a7da612b4a3f822df293e50bf043782eca1cb8
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Fri Jul 18 11:16:14 2014 +0200
i965/gen6/gs: Setup SOL surfaces for user-provided geometry shaders
Update gen6_gs_binding_table and gen6_sol_surface to use user-provided
geometry program information when present. This is necessary to implement
transform feedback support.
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=fda4470944762dddaff249ea36d6e21aa5f8e2ca
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Fri Jul 18 11:11:00 2014 +0200
i965/gen6/gs: implement transform feedback support in gen6_gs_visitor
This takes care of generating code required to handle transform feedback.
Notice that transform feedback isn't enabled yet, since that requires
additional setups in other parts of the code that will come in later patches.
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1f77bfce7debe34366942ec441eda38747a47f74
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Wed Jul 23 10:51:35 2014 +0200
i965/gen6/gs: Add an additional parameter to the FF_SYNC opcode.
We will use this parameter in later patches to provide information relevant
to transform feedback that needs to be set as part of the FF_SYNC message.
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3ea410972a9954babdcb6a0b1d4e5bc6f1ff61d2
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Wed Jul 23 12:56:53 2014 +0200
i965/gen6/gs: implement GS_OPCODE_FF_SYNC_SET_PRIMITIVES opcode
This opcode will be used when filling FF_SYNC header before
emitting vertices and their data.
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5933a08bd98d053a4cc5797d901bb399a8a5b470
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Fri Jul 18 10:47:15 2014 +0200
i965/gen6/gs: implement GS_OPCODE_SVB_SET_DST_INDEX opcode
This opcode generates code to copy the specified destination index
into subregister 5 of the MRF message header.
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e86ae1b0a32bbbe4fb02ae9cee5b447a75d7e27f
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Fri Jul 18 10:36:10 2014 +0200
i965/gen6/gs: implement GS_OPCODE_SVB_WRITE opcode
This opcode will be used when sending SVB WRITE messages to save
transform feedback outputs into Streamed Vertex Buffers.
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=66ec61c49f0e57ebe237de3ee5610c7fda972e9c
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Wed Jul 30 09:08:48 2014 +0200
i965/gen6/gs: Enable texture units and upload sampler state.
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6669fd0818a07f3bd8232ee72cf5e01d992b39f2
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Mon Jul 28 10:05:57 2014 +0200
i965/gen6/gs: Assign geometry shader VUE map properly.
So far in gen6 we only used geometry shaders to implement transform feedback
in vertex shaders, so we assumed that the VUE map for the geometry shader
stage was always the same as for the vertex shader stage. This is no longer
true now that we support user provided geometry shaders in gen6 too.
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=524ad6b901c3847db9d3528223d4ab2e2f517a1d
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Thu Jul 24 12:18:47 2014 +0200
i965/gen6/gs: Implement support for gl_PrimitiveIdIn.
For this we will need to move PrimitiveID information, delivered in the thread
payload in r0.1, to a separate register (we use GS_OPCODE_SET_PRIMITIVE_ID
for this), then map the corresponding varying slot to that register in the
setup_payload() method.
Notice that we cannot use a virtual register as the destination for the
PrimitiveID because we need to map all input attributes to hardware registers
in setup_payload(), which happens before virtual registers are mapped to
hardware registers. We could work around that issue if we were able to compute
the first non-payload register in emit_prolog() and move the PrimitiveID
information to that register, but we can't because at that point we still
don't know the final number uniforms that will be included in the payload.
So, what we do is to place PrimitiveID information in r1, which is always
delivered as part of the payload but its only populated with data
relevant for transform feedback when we set GEN6_GS_SVBI_PAYLOAD_ENABLE
in the 3DSTATE_GS state packet.
When we implement transform feedback, we wil make sure to move the value of r1
to another register before we overwrite it with the PrimitiveID.
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=024b7c0f33a6e8f59d8b3d9dd9f72d671f426890
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Thu Jul 24 12:14:27 2014 +0200
i965/gen6/gs: Implement GS_OPCODE_SET_PRIMITIVE_ID.
In gen6 the geometry shader payload includes the PrimitiveID information in
r0.1. When the shader code uses glPimitiveIdIn we will have to move this to
a separate hardware register where we can map this attribute. This opcode
takes the selected destination register and moves r0.1 there.
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c091804f4cd282bfc03b02a7ef6c72e5f42f6c76
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Mon Jul 21 11:48:42 2014 +0200
i965/gen6/gs: Handle the case where a geometry shader emits no output.
In gen6 we need to end the thread differently depending on whether we have
emitted at least one vertex or not. In case we did, the EOT message must
always include the COMPLETE flag or else the GPU hangs. If we have not
produced any output, however, we can't use the COMPLETE flag.
This would lead us to end the program with an ENDIF opcode, which we want
to avoid (and actually is not permitted since it hits an assertion), so
instead what we do is that we always request a new VUE handle every time we do
an URB WRITE, even for the last vertex we emit. With this we make sure that
whether we have emitted at least one vertex or none at all we have to finish the
thread without writing to the URB, which works for both cases by setting the
COMPLETE and UNUSED flags in the EOT message.
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c1b8a5155b4026ac6d0fdeae9afd12e489ef106b
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Mon Jul 21 09:18:52 2014 +0200
i965/gen6/gs: Make sure we complete the last primitive.
Just in case the GS algorithm does not call EndPrimitive() for the last
primitive produced. This is relevant only for non point outputs, since for
this we are already setting the PrimEnd flag on each vertex we emit.
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d93ca68666675392e632a5c0f99a33ff25a42e53
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Fri Jul 18 16:38:55 2014 +0200
i965/gen6/gs: Implement geometry shaders for outputs other than points.
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8411bf2c69136efcae594529f16e70ea0a22e271
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Wed Jul 16 09:10:35 2014 +0200
i965/gen6/gs: Add initial implementation for a gen6 geometry shader visitor.
Geometry shaders in gen6 are significantly different from gen7+ so it is better
to have them implemented in a different file rather than adding gen6 branching
paths all over brw_vec4_gs_visitor.cpp.
This commit adds an initial implementation that only handles point output, which
is the simplest case.
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5c30da184514f7d20c033a0c4d1f99626adaddd4
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Thu Jul 17 16:59:10 2014 +0200
i965: Generalize emit_urb_slot() to emit to any dst_reg.
In gen7+ we emit vertices as they come, however in gen6 geometry shaders we
have to buffer vertex data for all vertices and then emit it all in one go
at the end. To achieve this we need to generalize emit_urb_slot() to store
vertex data in general purpose registers and not only MRF registers.
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9b32fd0f704cf34172d3fd85934bfff7a6f77753
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Wed Jul 16 10:00:34 2014 +0200
i965: Provide means to create registers of a given size.
Implemented by Ilia Mirkin <imirkin at alum.mit.edu>.
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f373b7ed820024080838742f419bbca5fcbde2bf
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Thu Jul 17 08:54:03 2014 +0200
i965/gen6/gs: Implement GS_OPCODE_SET_DWORD_2.
We had GS_OPCODE_SET_DWORD_2_IMMED but this required its source argument to be
an immediate. In gen6 we need to set dword 2 of the URB write message header
from values stored in separate register, so we need something more flexible.
This change replaces GS_OPCODE_SET_DWORD_2_IMMED with GS_OPCODE_SET_DWORD_2.
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7ccd47d644962cbb6424a2e75de3b5317cbda62b
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Tue Jul 15 11:26:45 2014 +0200
i965/gen6/gs: Upload binding table for user-provided geometry shaders.
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5ac8294f9be525c03bdfa97ea123a333d71406b5
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Thu Jul 10 17:00:21 2014 +0200
i965/gen6/gs: Enable URB space for user-provided geometry shaders.
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c09ddf82ffa13173b55a1b51075be2671378c4ea
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Tue Jul 1 13:08:25 2014 +0200
i965/gen6/gs: Compute URB entry size for user-provided geometry shaders.
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=621685ad4c747cc67e1b6c7ba95fa59774196a54
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Wed Jul 9 15:32:57 2014 +0200
i965/gen6/gs: Add instruction URB flags to geometry shaders EOT message.
Gen6 seems to require that EOT messages include the complete flag too or else
the GPU hangs. We add will this flag to the instruction when we emit the
thread end opcode.
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2c85132e511bbef9a0965c69848981b1bffb5bad
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Wed Jul 9 16:28:30 2014 +0200
i965/gen6/gs: Implement GS_OPCODE_URB_WRITE_ALLOCATE.
Gen6 geometry shaders need to allocate URB handles for each new vertex they
emit after the first (the URB handle for the first vertex is obtained via the
FF_SYNC message).
This opcode adds the URB allocation mechanism to regular URB writes.
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d0bdd4ce983ddd52f9f4b70dced4e471c60a130c
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Wed Jul 9 08:46:17 2014 +0200
i965/gen6/gs: Implement GS_OPCODE_FF_SYNC.
This implements the FF_SYNC message required in gen6 geometry shaders to
get the initial URB handle.
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=406e04113fb23c514cc63bdab9a46476261d6f10
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Wed Jul 2 14:52:40 2014 +0200
i965/gs: Reuse gen6 constant push buffers setup code in gen7+.
The code required for gen6 and gen7+ is almost the same, so reuse it.
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=96012dfe80121c5d6f5f9c87149aa4ed1da567cb
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Thu Jul 3 16:33:32 2014 +0200
i965/gen6/gs: Setup constant push buffers for gen6 geometry shaders.
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=cf06136b634d5242759d015d694da3833469c416
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Wed Jul 30 15:17:15 2014 +0200
i965/gen6/gs: Set brw->gs.enabled to FALSE in gen6_blorp_emit_gs_disable()
See 7dfb4b2d00ddb8e5ee24d4c58eb9415dc4ccc21c for more details.
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=bc383cb55b9d342a77b44328cb4acb5bbdf4a80c
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Tue Jul 1 08:52:47 2014 +0200
i965/gen6/gs: use brw_gs_prog atom instead of brw_ff_gs_prog
This is needed to support user-provided geometry shaders, since the
brw_ff_gs_prog atom in gen6 only takes care of implementing transform feedback
for vertex shaders.
If there is no user-provided geometry shader the implementation falls back to
the original code.
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=dd376bdb254888f156e24d4360b6f6a408e2c5a2
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Tue Jul 1 08:43:57 2014 +0200
i965/gen6/gs: Skeleton for user GS program support
Currently, gen6 only uses geometry shaders for transform feedback so the state
we emit is not suitable to accomodate general purpose, user-provided geometry
shaders. This patch paves the way to add these support and the needed
3DSTATE_GS packet modifications for it.
Previous code that emitted state to implement transform feedback in gen6 goes
to upload_gs_state_adhoc_tf().
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=03164f6285b18a909d4de50d10c491e638bce8d7
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Tue Jul 1 08:52:31 2014 +0200
i965/gs: Use single dispatch mode as fallback to dual object mode when possible.
Currently, when a geometry shader can't use dual object mode we fall back to
dual instance mode, however, when invocations == 1, single dispatch mode is
more performant and equally efficient in terms of register pressure.
Single dispatch mode requires that the driver can handle interleaving of
input registers, but this is already supported (dual instance mode has
the same requirement). However, to take full advantage of single dispatch mode
to reduce register pressure we would also need the ability to store two
separate vec4 output values into vec8 registers, which would approximately
double our capacity to store temporary values, but currently the vec4 visitor
and generator classes do not support this, so at the moment register pressure
in single and dual instance modes is the same.
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
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