Mesa (master): nvc0/ir: allow tess eval output loads to be CSE'd

[Ilia Mirkin]

Module: Mesa
Branch: master
Commit: da89e75d9c6399c8fb0286460c91a77778c0eec9
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=da89e75d9c6399c8fb0286460c91a77778c0eec9

Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date:   Thu Apr 30 02:00:20 2015 -0400

nvc0/ir: allow tess eval output loads to be CSE'd

These only happen for gl_TessCoord which are constant.

Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>

---

 src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
index ad9bf6f..e9648aa 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
@@ -2518,6 +2518,8 @@ Instruction::isResultEqual(const Instruction *that) const
       case FILE_MEMORY_CONST:
       case FILE_SHADER_INPUT:
          return true;
+      case FILE_SHADER_OUTPUT:
+         return bb->getProgram()->getType() == Program::TYPE_TESSELLATION_EVAL;
       default:
          return false;
       }