[Mesa-dev] [PATCH] i965: Set UniformBufferOffsetAlignment to sizeof(vec4)

Paul Berry stereotype441 at gmail.com
Thu Feb 7 21:59:15 PST 2013


On 7 February 2013 19:25, Ian Romanick <idr at freedesktop.org> wrote:

> From: Ian Romanick <ian.d.romanick at intel.com>
>
> This matches the behavior of the Windows driver, but a bspec reference
> should would be nice.
>

I believe this is the bspec reference you're looking for:

>From the Ivy Bridge PRM, Vol4 Part1, p. 68 (2.12.2.1 SURFACE_STATE for most
messages):

    "Certain message types used to access surfaces have more stringent
alignment requirements. Please refer to the specific message documentation
for additional restrictions."

We use the "OWord block read" message to read uniforms, so we have to refer
to p. 233 (3.9.3 OWord Block Read/Write), which says:

    "The surface base address must be OWord-aligned."

Reviewed-by: Paul Berry <stereotype441 at gmail.com>


>
> NOTE: This is a candidate for the 9.0 and 9.1 branches.
>
> Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
> ---
>  src/mesa/drivers/dri/i965/brw_context.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_context.c
> b/src/mesa/drivers/dri/i965/brw_context.c
> index 1201565..9aa6abe 100644
> --- a/src/mesa/drivers/dri/i965/brw_context.c
> +++ b/src/mesa/drivers/dri/i965/brw_context.c
> @@ -360,6 +360,7 @@ brwCreateContext(int api,
>
>     ctx->Const.NativeIntegers = true;
>     ctx->Const.UniformBooleanTrue = 1;
> +   ctx->Const.UniformBufferOffsetAlignment = 16;
>
>     ctx->Const.ForceGLSLExtensionsWarn =
> driQueryOptionb(&intel->optionCache, "force_glsl_extensions_warn");
>
> --
> 1.7.11.7
>
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