[Mesa-dev] [PATCH 1/8] nv50/ir: add preliminary support for OP_ADD3

[Ilia Mirkin]

On Thu, Jun 30, 2016 at 6:26 PM, Samuel Pitoiset
<samuel.pitoiset at gmail.com> wrote:
> This instruction is new since SM50 (Maxwell) and allows to perform
> an add with three sources. Unfortunately, it only supports integers.
>
> Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
> ---
>  src/gallium/drivers/nouveau/codegen/nv50_ir.h                | 1 +
>  src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp        | 1 +
>  src/gallium/drivers/nouveau/codegen/nv50_ir_target.cpp       | 3 +++
>  src/gallium/drivers/nouveau/codegen/nv50_ir_target_gm107.cpp | 4 ++++
>  src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp  | 1 +
>  src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp  | 5 ++++-
>  6 files changed, 14 insertions(+), 1 deletion(-)
>
> diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir.h b/src/gallium/drivers/nouveau/codegen/nv50_ir.h
> index 94e54bb..6afe7c7 100644
> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir.h
> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir.h
> @@ -163,6 +163,7 @@ enum operation
>     OP_SHFL, // warp shuffle
>     OP_VOTE,
>     OP_BUFQ, // buffer query
> +   OP_ADD3,

I would highly recommend placing this op closer to the other arithmetic ops.

>     OP_LAST
>  };
>
> diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp
> index 6469f71..d88bdce 100644
> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp
> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp
> @@ -192,6 +192,7 @@ const char *operationStr[OP_LAST + 1] =
>     "shfl",
>     "vote",
>     "bufq",
> +   "add3",
>     "(invalid)"
>  };
>
> diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_target.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_target.cpp
> index cc98d32..8067787 100644
> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_target.cpp
> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_target.cpp
> @@ -57,6 +57,7 @@ const uint8_t Target::operationSrcNr[] =
>     3,                      // SHFL
>     1,                      // VOTE
>     1,                      // BUFQ
> +   3,                      // ADD3
>     0
>  };
>
> @@ -135,6 +136,8 @@ const OpClass Target::operationClass[] =
>     OPCLASS_OTHER,
>     // BUFQ
>     OPCLASS_OTHER,
> +   // ADD3
> +   OPCLASS_ARITH,
>     OPCLASS_PSEUDO // LAST
>  };
>
> diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_gm107.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_gm107.cpp
> index 92caeb2..5608b5e 100644
> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_gm107.cpp
> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_gm107.cpp
> @@ -61,6 +61,10 @@ TargetGM107::isOpSupported(operation op, DataType ty) const
>     case OP_DIV:
>     case OP_MOD:
>        return false;
> +   case OP_ADD3:
> +      if (isFloatType(ty))
> +         return false;
> +      break;
>     default:
>        break;
>     }
> diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp
> index b37ea73..e1a7963 100644
> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp
> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp
> @@ -437,6 +437,7 @@ TargetNV50::isOpSupported(operation op, DataType ty) const
>     case OP_EXTBF:
>     case OP_EXIT: // want exit modifier instead (on NOP if required)
>     case OP_MEMBAR:
> +   case OP_ADD3:
>        return false;
>     case OP_SAD:
>        return ty == TYPE_S32;
> diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp
> index 932ec39..f895019 100644
> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp
> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp
> @@ -147,7 +147,8 @@ static const struct opProperties _initProps[] =
>     { OP_SUSTP,   0x0, 0x0, 0x0, 0x0, 0x2, 0x0 },
>     { OP_SUCLAMP, 0x0, 0x0, 0x0, 0x0, 0x2, 0x2 },
>     { OP_SUBFM,   0x0, 0x0, 0x0, 0x0, 0x6, 0x2 },
> -   { OP_SUEAU,   0x0, 0x0, 0x0, 0x0, 0x6, 0x2 }
> +   { OP_SUEAU,   0x0, 0x0, 0x0, 0x0, 0x6, 0x2 },
> +   { OP_ADD3,    0x7, 0x0, 0x0, 0x0, 0x2, 0x2 },

Should probably update the commutative bitmask too (which is where
you'll find that moving it somewhere into range will be beneficial),
so that load propagation can swap it into the right place. [And, in a
later commit, teach that swap function to try to look at arg2 as
well.]

>  };
>
>  void TargetNVC0::initOpInfo()
> @@ -415,6 +416,8 @@ TargetNVC0::isOpSupported(operation op, DataType ty) const
>        return false;
>     if (op == OP_POW || op == OP_SQRT || op == OP_DIV || op == OP_MOD)
>        return false;
> +   if (op == OP_ADD3)
> +      return false;
>     return true;
>  }
>
> --
> 2.8.3
>
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