[Mesa-dev] [PATCH 0/5] Gallium support for TXF and TXL with level = 0

[Ilia Mirkin]

Why can't the compiler perform this opt? At least we do that in nouveau...

On Mar 7, 2017 7:33 AM, "Marek Olšák" <maraeo at gmail.com> wrote:

> Hi,
>
> These new TGSI opcodes are for better code generation in drivers. If you
> know the mipmap level or LOD is 0, you don't have to pass 0 to texture
> instructions on hardware that has dedicated instructions for level-zero
> fetches. This saves a temporary register that is usually required for
> the level or LOD parameter.
>
> This change surprisingly reduces VGPR register spilling for DiRT Showdown
> on radeonsi, but that doesn't seem to have a visible effect on performance.
> We can't make this improvement at the LLVM level though.
>
> Note that TXF with an MSAA target and TG4 already imply level = 0.
>
> Please review.
>
> Marek
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