[PATCH] drm/radeon/si_dpm: Limit clocks on HD86xx part

[StDenis, Tom]

Hi Alex,


No problem I'll submit that tomorrow morning.


Cheers,

Tom


________________________________
From: Deucher, Alexander
Sent: Thursday, October 13, 2016 15:19
To: 'Tom St Denis'; amd-gfx at lists.freedesktop.org
Cc: StDenis, Tom
Subject: RE: [PATCH] drm/radeon/si_dpm: Limit clocks on HD86xx part

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces at lists.freedesktop.org] On Behalf
> Of Tom St Denis
> Sent: Thursday, October 13, 2016 12:42 PM
> To: amd-gfx at lists.freedesktop.org
> Cc: StDenis, Tom
> Subject: [PATCH] drm/radeon/si_dpm: Limit clocks on HD86xx part
>
> Limit clocks on a specific HD86xx part to avoid
> crashes (while awaiting an appropriate PP fix).
>
> Signed-off-by: Tom St Denis <tom.stdenis at amd.com>

Reviewed-by: Alex Deucher <alexander.deucher at amd.com>

Care to send a patch for amdgpu as well?

Alex

> ---
>  drivers/gpu/drm/radeon/si_dpm.c | 6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/radeon/si_dpm.c
> b/drivers/gpu/drm/radeon/si_dpm.c
> index 89bdf20344ae..691f37b28b1a 100644
> --- a/drivers/gpu/drm/radeon/si_dpm.c
> +++ b/drivers/gpu/drm/radeon/si_dpm.c
> @@ -3021,6 +3021,12 @@ static void si_apply_state_adjust_rules(struct
> radeon_device *rdev,
>                max_sclk = 75000;
>                max_mclk = 80000;
>        }
> +     /* limit clocks on HD8600 series */
> +     if (rdev->pdev->device == 0x6660 &&
> +          rdev->pdev->revision == 0x83) {
> +             max_sclk = 75000;
> +             max_mclk = 80000;
> +     }
>
>        if (rps->vce_active) {
>                rps->evclk = rdev->pm.dpm.vce_states[rdev-
> >pm.dpm.vce_level].evclk;
> --
> 2.10.0
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <https://lists.freedesktop.org/archives/amd-gfx/attachments/20161013/d1b0daa1/attachment-0001.html>