[PATCH] drm/amdgpu/gfx8: move MEC doorbell range setting

[Zhu, Rex]

Patch was Tested-by and Reviewed-by:  Rex Zhu <Rex.Zhu at amd.com>


Best Regards

Rex

________________________________
From: amd-gfx <amd-gfx-bounces at lists.freedesktop.org> on behalf of Alex Deucher <alexdeucher at gmail.com>
Sent: Tuesday, April 11, 2017 1:02:02 AM
To: amd-gfx at lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH] drm/amdgpu/gfx8: move MEC doorbell range setting

It's global, not queue specific, so move it out of the
kiq register init function.

Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 26 ++++++++++++--------------
 1 file changed, 12 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index d3633cb..9bff7a9 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -4930,20 +4930,6 @@ static int gfx_v8_0_kiq_init_register(struct amdgpu_ring *ring)
         WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, mqd->cp_hqd_pq_wptr_poll_addr_lo);
         WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, mqd->cp_hqd_pq_wptr_poll_addr_hi);

-       /* enable the doorbell if requested */
-       if (ring->use_doorbell) {
-               if ((adev->asic_type == CHIP_CARRIZO) ||
-                   (adev->asic_type == CHIP_FIJI) ||
-                   (adev->asic_type == CHIP_STONEY) ||
-                   (adev->asic_type == CHIP_POLARIS10) ||
-                   (adev->asic_type == CHIP_POLARIS11) ||
-                   (adev->asic_type == CHIP_POLARIS12)) {
-                       WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER,
-                                               AMDGPU_DOORBELL_KIQ << 2);
-                       WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER,
-                                               AMDGPU_DOORBELL_MEC_RING7 << 2);
-               }
-       }
         WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, mqd->cp_hqd_pq_doorbell_control);

         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
@@ -5070,6 +5056,18 @@ static int gfx_v8_0_kiq_resume(struct amdgpu_device *adev)
                         goto done;
         }

+       if ((adev->asic_type == CHIP_CARRIZO) ||
+           (adev->asic_type == CHIP_FIJI) ||
+           (adev->asic_type == CHIP_STONEY) ||
+           (adev->asic_type == CHIP_POLARIS10) ||
+           (adev->asic_type == CHIP_POLARIS11) ||
+           (adev->asic_type == CHIP_POLARIS12)) {
+               WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER,
+                      AMDGPU_DOORBELL_KIQ << 2);
+               WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER,
+                      AMDGPU_DOORBELL_MEC_RING7 << 2);
+       }
+
         r = gfx_v8_0_kiq_kcq_enable(adev);
         if (r)
                 goto done;
--
2.5.5

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