[PATCH] drm/amdgpu: refine vce3.0 initialize.

[StDenis, Tom]

On my Carrizo, I have to NAK since monitoring the clocks I see GFX and VCE pegged high on a setup with a staging kernel .


Doing a test signal encode I see 1000 fences/sec being handled and GFX_POWER throttles (not idle or full) .  I don't see VCE load from SRBM_STATUS2 though ...


Something is up for sure.


I haven't tried HEAD~ (I last tried a 4.9 kernel about 15 commits ago) so I'll try that now.


Tom



________________________________
From: amd-gfx <amd-gfx-bounces at lists.freedesktop.org> on behalf of Rex Zhu <Rex.Zhu at amd.com>
Sent: Monday, January 9, 2017 08:34
To: amd-gfx at lists.freedesktop.org
Cc: Zhu, Rex
Subject: [PATCH] drm/amdgpu: refine vce3.0 initialize.

1. disable vce cg when vce hw initialize.
2. initizlize vce clock to 10KHz.
3: no need to set bypass clock to vce.

Change-Id: I18d5c2debc6688be201af8bb85022ac25020bd8f
Signed-off-by: Rex Zhu <Rex.Zhu at amd.com>
---
 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 18 +++---------------
 drivers/gpu/drm/amd/amdgpu/vi.c       | 32 +++++++++++++++++++++++++++++++-
 2 files changed, 34 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
index 5fb0b7f..eb99ee6 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
@@ -223,6 +223,9 @@ static int vce_v3_0_start(struct amdgpu_device *adev)
         struct amdgpu_ring *ring;
         int idx, r;

+       vce_v3_0_override_vce_clock_gating(adev, true); /* force all clocks on */
+       amdgpu_asic_set_vce_clocks(adev, 10000, 10000);
+
         ring = &adev->vce.ring[0];
         WREG32(mmVCE_RB_RPTR, ring->wptr);
         WREG32(mmVCE_RB_WPTR, ring->wptr);
@@ -701,17 +704,7 @@ static int vce_v3_0_process_interrupt(struct amdgpu_device *adev,
         return 0;
 }

-static void vce_v3_0_set_bypass_mode(struct amdgpu_device *adev, bool enable)
-{
-       u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);
-
-       if (enable)
-               tmp |= GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK;
-       else
-               tmp &= ~GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK;

-       WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);
-}

 static int vce_v3_0_set_clockgating_state(void *handle,
                                           enum amd_clockgating_state state)
@@ -720,11 +713,6 @@ static int vce_v3_0_set_clockgating_state(void *handle,
         bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
         int i;

-       if ((adev->asic_type == CHIP_POLARIS10) ||
-               (adev->asic_type == CHIP_TONGA) ||
-               (adev->asic_type == CHIP_FIJI))
-               vce_v3_0_set_bypass_mode(adev, enable);
-
         if (!(adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG))
                 return 0;

diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 16ba943..b9924e3 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -789,7 +789,37 @@ static int vi_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)

 static int vi_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
 {
-       /* todo */
+       int r, i;
+       struct atom_clock_dividers dividers;
+       u32 tmp;
+
+       r = amdgpu_atombios_get_clock_dividers(adev,
+                                              COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
+                                              ecclk, false, &dividers);
+       if (r)
+               return r;
+
+       for (i = 0; i < 100; i++) {
+               if (RREG32_SMC(ixCG_ECLK_STATUS) & CG_ECLK_STATUS__ECLK_STATUS_MASK)
+                       break;
+               mdelay(10);
+       }
+       if (i == 100)
+               return -ETIMEDOUT;
+
+       tmp = RREG32_SMC(ixCG_ECLK_CNTL);
+       tmp &= ~(CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK |
+               CG_ECLK_CNTL__ECLK_DIVIDER_MASK);
+       tmp |= dividers.post_divider;
+       WREG32_SMC(ixCG_ECLK_CNTL, tmp);
+
+       for (i = 0; i < 100; i++) {
+               if (RREG32_SMC(ixCG_ECLK_STATUS) & CG_ECLK_STATUS__ECLK_STATUS_MASK)
+                       break;
+               mdelay(10);
+       }
+       if (i == 100)
+               return -ETIMEDOUT;

         return 0;
 }
--
1.9.1

_______________________________________________
amd-gfx mailing list
amd-gfx at lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
amd-gfx Info Page - lists.freedesktop.org<https://lists.freedesktop.org/mailman/listinfo/amd-gfx>
lists.freedesktop.org
To see the collection of prior postings to the list, visit the amd-gfx Archives. Using amd-gfx: To post a message to all the list members, send email ...



-------------- next part --------------
An HTML attachment was scrubbed...
URL: <https://lists.freedesktop.org/archives/amd-gfx/attachments/20170109/a139864f/attachment-0001.html>