[PATCH v2] drm/amd/display: Fix bug use wrong pp interface

[Deucher, Alexander]

Acked-by: Alex Deucher <alexander.deucher at amd.com>

________________________________
From: amd-gfx <amd-gfx-bounces at lists.freedesktop.org> on behalf of Rex Zhu <Rex.Zhu at amd.com>
Sent: Wednesday, August 22, 2018 2:41:19 AM
To: amd-gfx at lists.freedesktop.org; Francis, David; Wentland, Harry
Cc: Zhu, Rex
Subject: [PATCH v2] drm/amd/display: Fix bug use wrong pp interface

Used wrong pp interface, the original interface is
exposed by dpm on SI and paritial CI.

Pointed out by Francis David <david.francis at amd.com>

v2: dal only need to set min_dcefclk and min_fclk to smu.
    so use display_clock_voltage_request interface,
    instand of update all display configuration.

Acked-by: Alex Deucher <alexander.deucher at amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu at amd.com>
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
index e5c5b0a..7811d60 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
@@ -480,12 +480,20 @@ void pp_rv_set_display_requirement(struct pp_smu *pp,
 {
         const struct dc_context *ctx = pp->dm;
         struct amdgpu_device *adev = ctx->driver_context;
+       void *pp_handle = adev->powerplay.pp_handle;
         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
+       struct pp_display_clock_request clock = {0};

-       if (!pp_funcs || !pp_funcs->display_configuration_changed)
+       if (!req || !pp_funcs || !pp_funcs->display_clock_voltage_request)
                 return;

-       amdgpu_dpm_display_configuration_changed(adev);
+       clock.clock_type = amd_pp_dcf_clock;
+       clock.clock_freq_in_khz = req->hard_min_dcefclk_khz;
+       pp_funcs->display_clock_voltage_request(pp_handle, &clock);
+
+       clock.clock_type = amd_pp_f_clock;
+       clock.clock_freq_in_khz = req->hard_min_fclk_khz;
+       pp_funcs->display_clock_voltage_request(pp_handle, &clock);
 }

 void pp_rv_set_wm_ranges(struct pp_smu *pp,
--
1.9.1

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