[PATCH] drm/amd/powerplay: Set higher SCLK&MCLK frequency than dpm7 in OD

[Zhu, Rex]

Acked-by:  Rex Zhu<rezhu at amd.com>

Best Regards
Rex

________________________________
From: amd-gfx <amd-gfx-bounces at lists.freedesktop.org> on behalf of Kenneth Feng <kenneth.feng at amd.com>
Sent: Tuesday, June 12, 2018 10:54 PM
To: amd-gfx at lists.freedesktop.org
Cc: Feng, Kenneth
Subject: [PATCH] drm/amd/powerplay: Set higher SCLK&MCLK frequency than dpm7 in OD

Fix the issue that SCLK&MCLK can't be set higher than dpm7 when
OD is enabled in SMU7.

Change-Id: If8249795739e29a063154cffce693b3c77cca151
Signed-off-by: Kenneth Feng <kenneth.feng at amd.com>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index b763c54..11e1762 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -3762,7 +3762,10 @@ static int smu7_generate_dpm_level_enable_mask(
         const struct smu7_power_state *smu7_ps =
                         cast_const_phw_smu7_power_state(states->pnew_state);

-       result = smu7_trim_dpm_states(hwmgr, smu7_ps);
+       /*skip the trim if od is enabled*/
+       if (!hwmgr->od_enabled)
+               result = smu7_trim_dpm_states(hwmgr, smu7_ps);
+
         if (result)
                 return result;

--
2.7.4

_______________________________________________
amd-gfx mailing list
amd-gfx at lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
amd-gfx Info Page - freedesktop.org<https://lists.freedesktop.org/mailman/listinfo/amd-gfx>
lists.freedesktop.org
Subscribing to amd-gfx: Subscribe to amd-gfx by filling out the following form. Use of all freedesktop.org lists is subject to our Code of Conduct.



-------------- next part --------------
An HTML attachment was scrubbed...
URL: <https://lists.freedesktop.org/archives/amd-gfx/attachments/20180612/5e0b2d10/attachment-0001.html>