[PATCH] drm/amdgpu/pp: fix copy paste typo in smu7_get_pp_table_entry_callback_func_v1

[Zhu, Rex]

Reviewed-by: Rex Zhu <Rex.Zhu at amd.com>



Best Regards

Rex



________________________________
From: amd-gfx <amd-gfx-bounces at lists.freedesktop.org> on behalf of Alex Deucher <alexdeucher at gmail.com>
Sent: Friday, June 29, 2018 2:38 AM
To: amd-gfx at lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH] drm/amdgpu/pp: fix copy paste typo in smu7_get_pp_table_entry_callback_func_v1

Should be using PCIELaneLow for the low clock level.

Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index e5c27d12aa49..077b79938528 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -3183,7 +3183,7 @@ static int smu7_get_pp_table_entry_callback_func_v1(struct pp_hwmgr *hwmgr,
         performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
                         state_entry->ucPCIEGenLow);
         performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
-                       state_entry->ucPCIELaneHigh);
+                       state_entry->ucPCIELaneLow);

         performance_level = &(smu7_power_state->performance_levels
                         [smu7_power_state->performance_level_count++]);
--
2.13.6

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