[PATCH 2/2] drm/amd/pp: Register smu irq for legacy asics

[Deucher, Alexander]

Series is:

Reviewed-by: Alex Deucher <alexander.deucher at amd.com>

________________________________
From: amd-gfx <amd-gfx-bounces at lists.freedesktop.org> on behalf of Rex Zhu <Rex.Zhu at amd.com>
Sent: Wednesday, March 21, 2018 1:51:28 AM
To: amd-gfx at lists.freedesktop.org
Cc: Zhu, Rex
Subject: [PATCH 2/2] drm/amd/pp: Register smu irq for legacy asics

Change-Id: I1927175adfecbcfe99908f06959f8c0a507d3278
Signed-off-by: Rex Zhu <Rex.Zhu at amd.com>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 33 ++++++++++++++++++++++++
 1 file changed, 33 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 8a81360..5323f74 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -3996,8 +3996,41 @@ static int smu7_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_f
                         PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm);
 }

+static const struct amdgpu_irq_src_funcs smu7_irq_funcs = {
+       .process = phm_irq_process,
+};
+
 static int smu7_register_irq_handlers(struct pp_hwmgr *hwmgr)
 {
+       struct amdgpu_irq_src *source =
+               kzalloc(sizeof(struct amdgpu_irq_src), GFP_KERNEL);
+
+       if (!source)
+               return -ENOMEM;
+
+       source->funcs = &smu7_irq_funcs;
+
+       if (hwmgr->thermal_controller.ucType ==
+                       hwmgr->default_thermal_ctrl_type ||
+               hwmgr->thermal_controller.ucType ==
+                       ATOM_TONGA_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL) {
+
+               amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev),
+                               AMDGPU_IH_CLIENTID_LEGACY,
+                               230,
+                               source);
+               amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev),
+                               AMDGPU_IH_CLIENTID_LEGACY,
+                               231,
+                               source);
+       }
+
+       /* Register CTF(GPIO_19) interrupt */
+       amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev),
+                       AMDGPU_IH_CLIENTID_LEGACY,
+                       83,
+                       source);
+
         return 0;
 }

--
1.9.1

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