[PATCH] drm/amdgpu: fix bug with IH ring setup

[Christian König]

Reviewed-by: Christian König <christian.koenig at amd.com>

Am 12.11.18 um 20:33 schrieb Deucher, Alexander:
>
> Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
>
>
>
> ------------------------------------------------------------------------
> *From:* amd-gfx <amd-gfx-bounces at lists.freedesktop.org> on behalf of 
> Yang, Philip <Philip.Yang at amd.com>
> *Sent:* Monday, November 12, 2018 2:20 PM
> *To:* amd-gfx at lists.freedesktop.org
> *Cc:* Yang, Philip
> *Subject:* [PATCH] drm/amdgpu: fix bug with IH ring setup
> The bug limits the IH ring wptr address to 40bit. When the system memory
> is bigger than 1TB, the bus address is more than 40bit, this causes the
> interrupt cannot be handled and cleared correctly.
>
> Change-Id: I3cd1b8ad046b38945372f2fd1a2d225624893e28
> Signed-off-by: Philip Yang <Philip.Yang at amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c 
> b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> index a99f717..a0fda6f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> @@ -129,7 +129,7 @@ static int vega10_ih_irq_init(struct amdgpu_device 
> *adev)
>          else
>                  wptr_off = adev->wb.gpu_addr + 
> (adev->irq.ih.wptr_offs * 4);
>          WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO, 
> lower_32_bits(wptr_off));
> -       WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI, 
> upper_32_bits(wptr_off) & 0xFF);
> +       WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI, 
> upper_32_bits(wptr_off) & 0xFFFF);
>
>          /* set rptr, wptr to 0 */
>          WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0);
> -- 
> 2.7.4
>
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