[PATCH] drm/amd/pp: Fix pp_sclk/mclk_od not work on smu7

[Deucher, Alexander]

Acked-by: Alex Deucher <alexander.deucher at amd.com>

________________________________
From: amd-gfx <amd-gfx-bounces at lists.freedesktop.org> on behalf of Rex Zhu <Rex.Zhu at amd.com>
Sent: Wednesday, October 24, 2018 10:55:08 AM
To: amd-gfx at lists.freedesktop.org; Russell, Kent
Cc: Zhu, Rex
Subject: [PATCH] drm/amd/pp: Fix pp_sclk/mclk_od not work on smu7

not update the dpm table with user's setting

Signed-off-by: Rex Zhu <Rex.Zhu at amd.com>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 6c99cbf..71cfbd4 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -3588,9 +3588,10 @@ static int smu7_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, cons
                         break;
         }

-       if (i >= sclk_table->count)
+       if (i >= sclk_table->count) {
                 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
-       else {
+               sclk_table->dpm_levels[i].value = sclk;
+       } else {
         /* TODO: Check SCLK in DAL's minimum clocks
          * in case DeepSleep divider update is required.
          */
@@ -3605,9 +3606,10 @@ static int smu7_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, cons
                         break;
         }

-       if (i >= mclk_table->count)
+       if (i >= mclk_table->count) {
                 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
-
+               mclk_table->dpm_levels[i-1].value = mclk;
+       }

         if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
                 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
--
1.9.1

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