[PATCH 2/6] drm/amdgpu: add more parameters and functions to amdgpu_umc structure

[Deucher, Alexander]

Please include a patch description.  Explain why you need the new interface.

Alex
________________________________
From: amd-gfx <amd-gfx-bounces at lists.freedesktop.org> on behalf of Tao Zhou <tao.zhou1 at amd.com>
Sent: Thursday, August 1, 2019 2:43 AM
To: amd-gfx at lists.freedesktop.org <amd-gfx at lists.freedesktop.org>; Zhang, Hawking <Hawking.Zhang at amd.com>; Li, Dennis <Dennis.Li at amd.com>; Chen, Guchun <Guchun.Chen at amd.com>; Pan, Xinhui <Xinhui.Pan at amd.com>
Cc: Zhou1, Tao <Tao.Zhou1 at amd.com>
Subject: [PATCH 2/6] drm/amdgpu: add more parameters and functions to amdgpu_umc structure

Signed-off-by: Tao Zhou <tao.zhou1 at amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h | 13 +++++++++++++
 drivers/gpu/drm/amd/amdgpu/umc_v6_1.h   |  2 ++
 2 files changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
index dfa1a39e57af..2604f5076867 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
@@ -22,15 +22,28 @@
 #define __AMDGPU_UMC_H__

 struct amdgpu_umc_funcs {
+       void (*ras_init)(struct amdgpu_device *adev);
         void (*query_ras_error_count)(struct amdgpu_device *adev,
                                         void *ras_error_status);
         void (*query_ras_error_address)(struct amdgpu_device *adev,
                                         void *ras_error_status);
+       void (*enable_umc_index_mode)(struct amdgpu_device *adev,
+                                       uint32_t umc_instance);
+       void (*disable_umc_index_mode)(struct amdgpu_device *adev);
 };

 struct amdgpu_umc {
         /* max error count in one ras query call */
         uint32_t max_ras_err_cnt_per_query;
+       /* number of umc channel instance with memory map register access */
+       uint32_t channel_inst_num;
+       /* number of umc instance with memory map register access */
+       uint32_t umc_inst_num;
+       /* UMC regiser per channel offset */
+       uint32_t channel_offs;
+       /* channel index table of interleaved memory */
+       const uint32_t *channel_idx_tbl;
+
         const struct amdgpu_umc_funcs *funcs;
 };

diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.h b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.h
index d25ae414f4d8..bddaf14a77f9 100644
--- a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.h
+++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.h
@@ -31,6 +31,8 @@
 #define UMC_V6_1_CHANNEL_INSTANCE_NUM           4
 /* number of umc instance with memory map register access */
 #define UMC_V6_1_UMC_INSTANCE_NUM               8
+/* total channel instances in one umc block */
+#define UMC_V6_1_TOTAL_CHANNEL_NUM     (UMC_V6_1_CHANNEL_INSTANCE_NUM * UMC_V6_1_UMC_INSTANCE_NUM)
 /* UMC regiser per channel offset */
 #define UMC_V6_1_PER_CHANNEL_OFFSET             0x800

--
2.17.1

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