[PATCH 3/9] drm/amdgpu: add hdp clock gating for Arcturus

[Feng, Kenneth]

Reviewed-by: Kenneth Feng <kenneth.feng at amd.com>


-----Original Message-----
From: amd-gfx [mailto:amd-gfx-bounces at lists.freedesktop.org] On Behalf Of Le Ma
Sent: Thursday, August 08, 2019 6:22 PM
To: amd-gfx at lists.freedesktop.org
Cc: Ma, Le <Le.Ma at amd.com>
Subject: [PATCH 3/9] drm/amdgpu: add hdp clock gating for Arcturus

[CAUTION: External Email]

Add hdp CGLS for Arcturus in set common clockgating function

Change-Id: I44e392fa5f7653908b36b0902e721d56eed3eb92
Signed-off-by: Le Ma <le.ma at amd.com>
---
 drivers/gpu/drm/amd/amdgpu/soc15.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 00758be..4fbaca3 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -1157,7 +1157,8 @@ static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable  {
        uint32_t def, data;

-       if (adev->asic_type == CHIP_VEGA20) {
+       if (adev->asic_type == CHIP_VEGA20 ||
+               adev->asic_type == CHIP_ARCTURUS) {
                def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL));

                if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) @@ -1289,6 +1290,10 @@ static int soc15_common_set_clockgating_state(void *handle,
                soc15_update_rom_medium_grain_clock_gating(adev,
                                state == AMD_CG_STATE_GATE ? true : false);
                break;
+       case CHIP_ARCTURUS:
+               soc15_update_hdp_light_sleep(adev,
+                               state == AMD_CG_STATE_GATE ? true : false);
+               break;
        default:
                break;
        }
--
2.7.4

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